FPGA/ASIC Design Engineer — Final Secret Clearance

Entegee; United States; On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

401K plan

Paid Leave

Commuter Benefits

Job summary

Entegee seeks a highly skilled FPGA/ASIC engineer with a Final Secret clearance to lead front-end design tasks. The role requires strong VHDL/Verilog proficiency, deep digital circuit knowledge, and experience with major FPGA platforms and design tools.

The candidate will analyze architecture, optimize resources, ensure timing closure, and troubleshoot complex FPGA/ASIC systems while collaborating across teams.

Qualifications

• Bachelor’s degree in STEM with 5+ years of experience or advanced degree with 3+ years.
• Active Final Secret Security Clearance.
• 3+ years in FPGA development, ASIC front-end design, or related field.
• Proficient in VHDL and/or Verilog for FPGA/ASIC design.
• Experience with digital circuit architecture, timing, and optimization.
• Familiar with FPGA platforms (AMD/Xilinx, Altera, Microchip) and tools (Vivado, Quartus, Libero).
• Strong analytical, debugging, and troubleshooting abilities for FPGA/ASIC systems.
• Knowledge of Git and Subversion version control.

Skills

FPGA/ASIC design experience

VHDL/Verilog proficiency

Digital circuit design & timing

Analytical & debugging skills

Security clearance (Final Secret)

Education

Bachelor’s degree in STEM

Advanced degree in related discipline

Tools

Vivado

Quartus

Libero

Job description

Entegee seeks a highly skilled FPGA/ASIC engineer with a Final Secret clearance to lead front-end design tasks. The role requires strong VHDL/Verilog proficiency, deep digital circuit knowledge, and experience with major FPGA platforms and design tools.

The candidate will analyze architecture, optimize resources, ensure timing closure, and troubleshoot complex FPGA/ASIC systems while collaborating across teams.