Contract FPGA Engineer: Versal/Verilog, On-Site

Boeing; El Segundo (CA); On-site; USD 145,000 - 158,000; Full time

Benefits offered by this job

Medical

Dental

Vision

401K

Job summary

Boeing is seeking a contract FPGA/ASIC design engineer in California. You will own top-level FPGA design, add blocks, and integrate IP cores, with emphasis on timing closure and constrained synthesis using Vivado for Versal/Ultrascale devices.

You will program FPGAs, collaborate with system engineering for HW/SW integration, and participate in testing to deliver a fully functioning system. On-site work in El Segundo is required.

Qualifications

• 5+ years of FPGA and/or ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency required.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).
• Active U.S. secret security clearance

Responsibilities

• Inherit FPGA top-level design and add new functional blocks and interfaces.
• Update constraint files, perform synthesis, simulation, and Place & Route to ensure timing closure and design integrity.
• Program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.
• Collaborate with system engineering to support hardware/software integration and testing.
• On-site work is required.

Skills

FPGA/ASIC design

Vivado

Versal family

Verilog/SystemVerilog

Timing closure

Security clearance

Job description

Boeing is seeking a contract FPGA/ASIC design engineer in California. You will own top-level FPGA design, add blocks, and integrate IP cores, with emphasis on timing closure and constrained synthesis using Vivado for Versal/Ultrascale devices.

You will program FPGAs, collaborate with system engineering for HW/SW integration, and participate in testing to deliver a fully functioning system. On-site work in El Segundo is required.