Formal Verification CAD Engineer: Flow & Debug

Apple Inc.; Austin (TX); On-site; USD 129,000 - 195,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock purchase plan

Relocation assistance

Job summary

Apple Inc. is seeking a Formal Verification CAD engineer in Cupertino to design and maintain verification flows for next-generation SoCs.

You will develop software for the CAD team and collaborate with internal teams to enable scalable, reliable verification across Apple devices. You will work on property checking, low-power, connectivity checks, SEC, and coverage, while developing CI/CD pipelines and large-scale compute management.

Qualifications

• Scripting in Python, Perl, Kotlin or TCL.
• Software development with test in mind.
• Knowledge of Verilog and SystemVerilog.
• BS and 3+ years of relevant industry experience.

Responsibilities

• Develop, maintain, and enhance an existing formal verification tool execution system.
• Support Jasper reset analysis, SEC, and formal proofing flows.
• Debug vendor tool problems and collaborate with design/formal verification teams to solve issues.

Skills

Python

Perl

Kotlin

TCL

Verilog

SystemVerilog

Education

BS in a related field

Tools

Jasper

VC Formal

Job description

Apple Inc. is seeking a Formal Verification CAD engineer in Cupertino to design and maintain verification flows for next-generation SoCs.

You will develop software for the CAD team and collaborate with internal teams to enable scalable, reliable verification across Apple devices. You will work on property checking, low-power, connectivity checks, SEC, and coverage, while developing CI/CD pipelines and large-scale compute management.