Experienced Formal Verification CAD Engineer

Apple Inc.; Cupertino (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. in Cupertino is seeking a Formal Verification CAD engineer within the Silicon Technologies group to design and maintain verification flows for next-generation SoCs.

You will collaborate with the CAD team to build scalable tools, improve regression coverage, and help ensure high reliability across Apple’s power-efficient processors. The role emphasizes scripting (Python, Perl, Kotlin, TCL), Verilog/SystemVerilog, and testing-minded software development, with opportunities to optimize

Qualifications

• Experience scripting in Python, Perl, Kotlin or TCL.
• Software development experience with test in mind.
• Knowledge in Verilog and SystemVerilog.
• BS degree and 3+ years of relevant industry experience.

Responsibilities

• Develop, maintain, and enhance a system executing a formal verification tool.
• Support Jasper reset analysis, SEC and formal proofing flows.
• Debug vendor tool problems and collaborate with designers/formal verification teams.

Skills

Python

Perl

Kotlin

TCL

Software Development with Test mindset

Verilog

SystemVerilog

Education

BS in Electrical Engineering or Computer Science

Tools

Jasper

VC Formal

Job description

Apple Inc. in Cupertino is seeking a Formal Verification CAD engineer within the Silicon Technologies group to design and maintain verification flows for next-generation SoCs.

You will collaborate with the CAD team to build scalable tools, improve regression coverage, and help ensure high reliability across Apple’s power-efficient processors. The role emphasizes scripting (Python, Perl, Kotlin, TCL), Verilog/SystemVerilog, and testing-minded software development, with opportunities to optimize