SoC Formal Verification Engineer — Security & Microarchitecture

Apple Inc.; Santa Clara (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Apple Inc. is seeking a Formal Verification Engineer to drive complete formal verification for multiple design blocks and IPs within Apple Silicon. You will work with Security Enclave engineers to define micro-architecture specifications and craft verification plans to prove properties and uncover bugs.

You will develop reusable formal models, optimize verification code, and advance correct-by-construction methodologies for high‑quality, power‑efficient processors and SoCs.

Qualifications

• A minimum of a bachelor's degree and a minimum of 3 years of relevant industry experience in silicon validation software engineering or related field.

Responsibilities

• Work with Security Enclave design engineers to develop a formal micro-architecture specification.
• Develop comprehensive formal verification test plans including security requirement verification.
• Prove properties of the design, find design bugs, and collaborate with design teams to improve micro-architecture.
• Craft novel solutions for modeling security attacks and proving robustness of complex designs.
• Develop reusable and optimized formal models and verification code base.
• Architect correct-by-construction design methodologies for improved verification efficiency.

Skills

Formal verification

Security Enclave

SVA/PSL

SoC design

Debugging

Scripting

Education

Bachelor's degree in Electrical Engineering or related

Tools

EDA tools

Formal verification tools

Tool development

Job description

Apple Inc. is seeking a Formal Verification Engineer to drive complete formal verification for multiple design blocks and IPs within Apple Silicon. You will work with Security Enclave engineers to define micro-architecture specifications and craft verification plans to prove properties and uncover bugs.

You will develop reusable formal models, optimize verification code, and advance correct-by-construction methodologies for high‑quality, power‑efficient processors and SoCs.