Formal Verification Engineer: SoC Security & IP (Equity)

Apple Inc.; Cupertino (CA); On-site; USD 129,000 - 195,000; Full time

Job summary

Apple Inc. in Cupertino, California, is seeking a Formal Verification Engineer to drive complete formal verification for multiple IPs within Apple Silicon.

You will work on security-focused verification for CPUs, memory controllers, and related IPs, interfacing with design teams to ensure robust micro-architectures and secure enclaves. As part of the Silicon Technologies group, you will craft verification plans, prove properties, and develop reusable models and tools to accelerate verification.

Qualifications

• Experience in silicon validation software engineering or related field.
• Hands on experience with VLSI and digital logic design and verification techniques or formal methods.
• Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular designs.
• Detail oriented approach and desire to overcome challenges is required.
• Formal Method or Formal Verification technologies knowledge is a plus.
• Knowledge and experience in interpreting hardware specifications.
• Temporal logic assertion-based languages such as SVA or PSL.
• Experience in using EDA formal tools and tool development experience is plus.
• Proficiency in any scripting language with excellent debugging skills.
• Excellent interpersonal skills.
• Passionate about developing world-class/innovative formal verification solutions.
• Exposure to CPU instruction-set architectures, memory consistency or cache coherence principles

Responsibilities

• Working with Apple Silicon's world-class Security Enclave design engineers to develop a formal micro-architecture specification
• Developing comprehensive formal verification test plan that includes unique security requirement verification
• Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture.
• Crafting novel and creative solutions for modelling security attacks and proving robustness of complex design micro-architectures
• Developing and implementing re-usable and optimized formal models and verification code base
• Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.

Job description

Apple Inc. in Cupertino, California, is seeking a Formal Verification Engineer to drive complete formal verification for multiple IPs within Apple Silicon.

You will work on security-focused verification for CPUs, memory controllers, and related IPs, interfacing with design teams to ensure robust micro-architectures and secure enclaves. As part of the Silicon Technologies group, you will craft verification plans, prove properties, and develop reusable models and tools to accelerate verification.