Senior Serdes System Design Engineer/Architect

Broadcom; Austin (TX); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Annual bonus (discretionary)

Equity grants & annual equity awards

ESPP

401(k) with company match

Employee Assistance Program (EAP)

Paid holidays

Paid sick leave

Paid vacation

Medical, dental, vision plans

Job summary

Broadcom is seeking a DSP/Systems Design Engineer for high-speed Serdes in the PLP Division in Austin. You will contribute to design, verification, and implementation of advanced signal processing for 100G+ Serdes in silicon technology nodes, collaborating with analog/digital teams and validating in lab environments.

You will participate in IEEE/OIF standard activities, develop channel models, and create test plans, firmware, and system models for verification.

Qualifications

• B.S.E.E. + 8+ years or M.S.E.E. + 6 years minimum.
• Expert knowledge in Communication Theory.
• Expert knowledge in Digital Signal Processing algorithms.
• Working knowledge of Analog circuit behavior.
• Working knowledge of Transmission line theory and s-parameter.
• Expert in MATLAB, C/C++ programming.
• Hands-on lab experience.
• Experience with high-speed CDR PLLs is highly preferred.
• Experience with wireline equalization techniques is a plus.
• RTL coding is a plus.
• Knowledge of IEEE 802.3/OIF Serdes standards and PCIe Gen6/Gen7 is a plus.

Responsibilities

• Develop channel models and simulations to define Serdes architecture.
• Define and document signal processing block requirements and lab test plans.
• Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
• Create system-level simulation suites to evaluate architectural tradeoffs.
• Collaborate with RTL team for vector matching verification.
• Develop, test and debug firmware for physical layer functionality.
• Lab testing and debugging of Serdes.
• Prepare documentation and customer support materials.
• Support marketing with customer meetings and collateral.

Skills

Communication Theory

Digital Signal Processing

Analog Circuit Behavior

Transmission Line Theory

MATLAB

C/C++ Programming

Lab Experience

CDR PLLs

Wireline Equalization

RTL Coding

Serdes Standards (IEEE/PCIe)

Education

B.S.E.E.

M.S.E.E.

Tools

MATLAB

C/C++

Job description

Job Description

This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+.

The types of algorithms that will be implemented include PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-idealities.

You will be collaborating closely with analog & digital designers to successfully implement the algorithms in advanced silicon technology nodes and work with DVT/lab engineers to validate your designs for high-volume production.

You will support the group contribute to the development of next-generation wireline communications standards at standard bodies such as IEEE and OIF.

Responsibilities

• Develop channel models and run simulations to help define Serdes architecture
• Define and document signal processing block requirements, architecture, and lab test plan
• Develop bit-exact MATLAB and C/C++ system models for simulation and verification
• Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs
• Work with the design team to perform vector matching verification with RTL simulations
• Develop, test, and debug firmware associated with physical layer functionality
• Lab testing and debug of Serdes
• Documentation/application note development and customer support
• Support marketing group with customer meetings and collateral

Job Requirements

• B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years required
• Expert knowledge in Communication Theory
• Expert knowledge in Digital Signal Processing algorithms
• Working knowledge of Analog circuit behavior
• Working knowledge of Transmission line theory and s-parameter
• Expert in MATLAB, C/C++ programming
• Good hands-on skills in the lab
• Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.
• Experience in equalization techniques for wireline communication applications such as read-channel is also a very big plus.
• RTL coding is a plus
• Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards is a plus

Compensation And Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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