Senior FPGA/ASIC Logic Architect – Remote

Ciklum; United States; Remote; USD 52,000 - 88,000; Full time

Benefits offered by this job

Medical subscription

Meal tickets

Remote-friendly policy

Job summary

Ciklum is seeking an Expert Logic Design Engineer to lead architecture, RTL implementation, and optimization of FPGA/ASIC digital subsystems. You will work with system architects, verification engineers, and software teams to deliver high-performance IP with ultra-low latency and robust timing closure.

The role emphasizes architectural trade-offs, cross-disciplinary collaboration, and hands-on design leadership in a fast-paced, technology-driven environment, including opportunities to work

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or equivalent.
• 6+ years of FPGA/ASIC digital logic design experience.
• Expert-level SystemVerilog RTL design (mandatory).
• Proven ability to deliver complex digital IP or subsystems end-to-end.

Responsibilities

• Lead architecture, microarchitecture, and RTL for high-performance FPGA/ASIC subsystems.
• Design and optimize ultra-low-latency digital logic with SystemVerilog.
• Drive end-to-end digital IP development from requirements to integration.
• Make architectural decisions to optimize timing, latency, and power.
• Address timing closure, clock-domain crossing, and critical-path issues.
• Develop digital processing and control architectures including DSP pipelines.
• Define hardware-software interfaces for efficient system integration.
• Collaborate with verification to define strategies and coverage.
• Review RTL designs and guide implementation risks.
• Contribute to reusable digital IP for future ASICs.

Skills

SystemVerilog

RTL design

Timing closure

CDC

Digital architecture

Verification

Technical leadership

Education

BSc/MSc in Electrical or Computer Engineering

Tools

AMD Vivado

Synopsys VCS

Questa

Job description

Ciklum is seeking an Expert Logic Design Engineer to lead architecture, RTL implementation, and optimization of FPGA/ASIC digital subsystems. You will work with system architects, verification engineers, and software teams to deliver high-performance IP with ultra-low latency and robust timing closure.

The role emphasizes architectural trade-offs, cross-disciplinary collaboration, and hands-on design leadership in a fast-paced, technology-driven environment, including opportunities to work