Mid Level FPGA Engineer

0 Base Design LLC; Raleigh (NC); Hybrid; USD 90,000 - 130,000; Full time

Benefits offered by this job

Restricted Stock and Options

401(k)

Health insurance

Paid time off

401(k) matching

Job summary

0 Base Design LLC in Raleigh, NC is seeking a Mid-Level FPGA/RTL Design Engineer with 4 to 5+ years to own design, implementation, and verification for FPGA platforms (Xilinx and Lattice). You will write RTL in Verilog and VHDL across architecture, simulation, synthesis, timing closure and hardware bring-up.

The role emphasizes lab-based debugging, hardware/software integration, and collaboration with embedded software engineers; hybrid schedule with up to 2 days remote; DoD Secret clearance

Qualifications

• Minimum 4–5+ years of RTL design experience in Verilog and VHDL.
• Proven track record with Xilinx and Lattice FPGA families.
• Strong understanding of clock domain crossing and timing closure.
• Experience with testbenches and functional simulations.
• Lab-based debugging, hardware/software integration, and JTAG tools.
• Knowledge of high-speed interfaces (PCIe, SERDES, DDR, SPI, I2C, Ethernet).

Responsibilities

• RTL Design & Implementation: Design and implement digital logic in Verilog and VHDL for FPGA-based systems, targeting Xilinx and Lattice device families.
• Verification: Develop testbenches and perform functional simulation to validate design before hardware bring-up.
• Synthesis & Timing Closure: Drive designs through synthesis, place-and-route, and timing closure using Vivado and Lattice toolchains.
• Hardware/Software Integration: Collaborate with embedded software engineers to define hardware-software interfaces and support firmware bring-up.
• Hardware Bring-up & Debug: Lead lab-based debugging using ILAs, logic analyzers, oscilloscopes, and JTAG tools.

Skills

RTL Design

Digital Logic

FPGA

Embedded C/C++ familiarity

Verilog

VHDL

Education

Bachelor of Science in Electrical Engineering or Computer Engineering

Tools

Vivado

Lattice Diamond/Radiant

Lattice Propel

Job description

Benefits:

• Restricted Stock and Options
• 401(k)
• Health insurance
• Paid time off
• 401(k) matching

Location: Raleigh, NC (Hybrid – Up to 2 days remote) Job Type: Full-Time Experience Level: Mid-Level (4 to 5+ years) Security Requirement: Ability to obtain/maintain a DoD Secret Clearance

Position Summary

We are seeking a skilled and motivated Mid-Level FPGA/RTL Design Engineer with a minimum of 4 to 5+ years of experience to join our engineering team in Raleigh, NC. In this role, you will own the design, implementation, and verification of digital logic targeting Xilinx and Lattice FPGA platforms, writing RTL in both Verilog and VHDL across the full development lifecycle — from architecture and simulation through synthesis, timing closure, and hardware bring-up.

This position focuses heavily on producing robust, well-verified RTL and supporting the hardware/software boundary. You will balance digital design with hands-on technical execution, including lab-based debug, hardware-software integration, and system-level troubleshooting alongside embedded software engineers.

Work Schedule & Security Requirements

Schedule: Hybrid environment based out of our Raleigh, NC facility, offering flexibility for up to 2 days of remote work per week. Remote work is subject to manager approval and prior authorization based on project milestones. Note that hands-on lab work, hardware debugging, and system bring-up will require an on-site presence.

Clearance: Ability to obtain and maintain a Department of Defense (DoD) Secret Security Clearance (or equivalent agency clearance).

Key Responsibilities

• RTL Design & Implementation: Design and implement digital logic in Verilog and VHDL for FPGA-based systems, targeting Xilinx (e.g., Artix, Kintex, Zynq/Zynq UltraScale+, Versal) and Lattice (e.g., ECP5, CrossLink, Nexus/CertusPro) device families.
• Verification: Develop testbenches and perform functional simulation (Vivado Simulator, CocoTB, or similar) to validate design correctness prior to hardware bring-up.
• Synthesis & Timing Closure: Drive designs through synthesis, place-and-route, and timing closure using Vivado and Lattice Diamond/Radiant toolchains.
• Hardware/Software Integration: Collaborate closely with embedded software engineers to define and validate hardware-software interfaces (register maps, DMA, interrupts, memory-mapped peripherals) and support firmware bring-up on FPGA-hosted processors.
• Hardware Bring-up & Debug: Lead lab-based debug using ILAs, logic analyzers, oscilloscopes, and JTAG tools; troubleshoot systemic issues crossing the hardware/firmware boundary.
• Interface & Requirements Support: Interface RTL with high-speed peripherals (DDR, SPI, I2C, UART, Ethernet, PCIe, SERDES/transceivers) and support Interface Control Documents (ICDs) where FPGA I/O touches other subsystems.
• Documentation & Reviews: Participate in design reviews and produce clear documentation (design specs, verification plans, timing/constraint reports).
• Design Methodology: Contribute to improving internal RTL design methodology, IP reuse, and verification practices.

Required Qualifications

• Education: Bachelor of Science (BS) degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Experience: A minimum of 4 to 5+ years of professional experience writing RTL in both Verilog and VHDL, with demonstrated work on both Xilinx and Lattice FPGA platforms.
• Toolchain Proficiency: Hands-on proficiency with Vivado and Lattice Diamond/Radiant (or Lattice Propel).
• Digital Design Fundamentals: Solid understanding of clock domain crossing, timing closure, synchronous/asynchronous design, FSMs, and pipelining.
• Verification: Experience writing testbenches and running simulations for functional verification.
• Embedded Software Familiarity: Working familiarity with embedded C/C++ sufficient to collaborate on hardware-software interfaces, debug firmware-driver issues, and support bring-up of soft-core or hard processors (e.g., MicroBlaze, Zynq PS).
• Lab Skills: Comfortable using oscilloscopes, logic analyzers, and JTAG-based tools for hardware debug.

Preferred Skills

• High-Speed Interfaces: Experience with SERDES/transceiver design (Aurora, PCIe, MGT-based links).
• Scripting & Automation: Experience in Python or TCL for build automation, test automation, or tool flow scripting.
• Advanced Verification: Exposure to constrained-random or formal verification methodologies (UVM, SVA).
• Embedded/OS Exposure: Experience with embedded Linux bring-up, RTOS integration, or device driver development.
• Version Control & CI: Familiarity with Git and CI/build pipelines for hardware projects.
• Standards & Compliance: Exposure to design standards applicable to defense/aerospace hardware (e.g., IPC, ISO, or military standards).
• Signal Integrity: Working knowledge of signal integrity and PCB-level considerations affecting FPGA I/O.

Flexible work from home options available.