Ethernet MAC & Network Datapath RTL Architect

Architect Labs; Palo Alto (CA); On-site; USD 190,000 - 240,000; Full time

Job summary

Architect Labs in Palo Alto seeks a Member of the Technical Staff to own the AI-driven microarchitecture and RTL for high‑performance networking subsystems destined for production silicon. You will define block-level microarchitectural specs for Ethernet MAC engines, packet processing datapaths, and interfaces, ensuring line‑rate performance and tight SoC integration.

Collaborate with DV, SW, and ML teams; support FPGA prototyping on Xilinx.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or closely related field.
• 5+ years RTL design with networking or packet-processing silicon experience.
• IEEE 802.3 Ethernet standards familiarity including MAC/PCS.
• Hands-on Ethernet MAC design: Tx/Rx pipelines, FCS, VLAN, jumbo frames.
• Clear, synthesizable SystemVerilog RTL with good design hygiene.
• Knowledge of AMBA protocols and clock domain crossings.
• Python for design automation and regression tooling.
• PPA ownership from RTL to timing/area/power closure.

Responsibilities

• Own the network datapath RTL end-to-end from MAC to timing closure.
• Design and implement Ethernet MAC engines for multi‑speed operation.
• Architect packet processing datapaths including DMA interfaces.
• Collaborate with the principal architect to refine microarchitectural specs.
• Define and maintain interface specs (MII/GMII/XGMII, AXI-Stream).
• Build RTL infrastructure and regression flows for AI‑driven design.
• Work with DV to verify protocol compliance and coverage plans.
• Collaborate with SW/ML to improve the AI flow for networking.

Skills

RTL design

Ethernet MAC

SystemVerilog

Packet datapath

AMBA AXI/AXI-Stream

Python

PPA ownership

Education

Bachelor’s in Electrical/Computer Engineering

Tools

Xilinx Vivado

SVA (SystemVerilog Assertions)

UVM

Job description

Architect Labs in Palo Alto seeks a Member of the Technical Staff to own the AI-driven microarchitecture and RTL for high‑performance networking subsystems destined for production silicon. You will define block-level microarchitectural specs for Ethernet MAC engines, packet processing datapaths, and interfaces, ensuring line‑rate performance and tight SoC integration.

Collaborate with DV, SW, and ML teams; support FPGA prototyping on Xilinx.