Senior RTL Network Architect - 100G Ethernet MAC & Datapath

Architect; Palo Alto (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Architect Labs is seeking a senior RTL Design engineer to own the AI-driven, high-speed Ethernet MAC datapath. You will define microarchitecture, implement MAC/PCS logic, and shape packet processing pipelines for production silicon.

Collaboration with DV, SW, and ML teams is essential, along with FPGA prototyping for early validation. The role requires 5+ years of RTL experience in networking silicon, strong SystemVerilog, and Python tooling to support design automation and regression testing.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or closely related field.
• 5+ years RTL design experience, with at least one advanced-node tapeout in networking or packet-processing silicon.

Responsibilities

• Own the network datapath RTL end-to-end across design, lint, CDC, and timing closure.
• Design and implement Ethernet MAC engines (MAC/PCS, FCS, flow control, rate adaptation).
• Architect packet processing datapaths with Tx/Rx FIFO, DMA interfaces, and QoS scheduling.
• Collaborate with DV, SW, and ML teams to refine microarchitecture and AI-driven design flow.
• Support FPGA prototyping on Xilinx platforms for early validation.

Skills

RTL design

Python

SystemVerilog

Networking knowledge

Education

Bachelor’s/Master’s/PhD in Electrical/Computer Engineering

Tools

Xilinx Vivado/Vitis

Job description

Architect Labs is seeking a senior RTL Design engineer to own the AI-driven, high-speed Ethernet MAC datapath. You will define microarchitecture, implement MAC/PCS logic, and shape packet processing pipelines for production silicon.

Collaboration with DV, SW, and ML teams is essential, along with FPGA prototyping for early validation. The role requires 5+ years of RTL experience in networking silicon, strong SystemVerilog, and Python tooling to support design automation and regression testing.