Founding Member, AI-Driven RTL & Microarchitecture

Architect Labs; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Competitive salary

Meaningful equity stake

Autonomy with impact

Job summary

Architect Labs is seeking a founding member of the Technical Staff for the RTL Design team in Palo Alto. You will own the AI-driven microarchitecture and RTL design of critical SoC blocks, defining block-level specs and leading end-to-end flows for production silicon.

You will collaborate with principal architects, DV, SW, and ML teams, driving interface standards (AXI), system-level timing, and power optimizations. Strong leadership and block-owner experience are essential.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience, worked on specialized HW accelerators.
• Strong SystemVerilog, synthesizable RTL with modular design and configurability.
• Hands-on block-level compute datapaths and data movement (MAC arrays, vector units, interconnects, DMA engines).
• Solid grasp of SoC methodology: synthesis, timing constraints, clock-domain crossings, reset strategies, AMBA protocols, power management.

Responsibilities

• Own AI-driven RTL design flow end-to-end from frontend to tape-in.
• Refine microarchitectural specs with principal architect and resolve trade-offs.
• Define and maintain interface specifications (AXI/AXI-Stream).
• Build and maintain RTL infrastructure for AI-driven flow and regression.
• Support DV bring-up with reference models, assertions, test-plans, and documentation.
• Collaborate with SW/ML teams to improve AI flow based on experience.
• Support FPGA prototyping for early functional validation.

Skills

RTL Design

SystemVerilog

Python

Leadership

DDR/NoC/AXI

PPA ownership

Education

Bachelor's/Master's/PhD in EE/CE

Tools

Vivado

Vitis

AXI

Job description

Architect Labs is seeking a founding member of the Technical Staff for the RTL Design team in Palo Alto. You will own the AI-driven microarchitecture and RTL design of critical SoC blocks, defining block-level specs and leading end-to-end flows for production silicon.

You will collaborate with principal architects, DV, SW, and ML teams, driving interface standards (AXI), system-level timing, and power optimizations. Strong leadership and block-owner experience are essential.