Design Verification Emulation, Hardware

River AI; Austin, Palo Alto (TX, CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, vision

Relocation support

Job summary

River AI seeks an emulation-focused design verification engineer to drive IP/SoC verification on emulation platforms. You will translate architectural definitions into emulation workloads, run tests, and partner with DV block owners on debug and signoff.

You will build models and infrastructure to support this work, ensuring traceable results across teams. The role requires expertise in SystemVerilog, C/C++, and scripting, with hands-on experience on Palladium/Protium or ZeBu/HAPS.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience with verification planning and running DV workflows for emulation or simulation acceleration.

Responsibilities

• Translate IP/SoC verification plans into emulation workloads and acceptance criteria.
• Develop and maintain emulation models, test components, and infrastructure.
• Lead emulation signoff input to IP/SoC verification signoff.
• Collaborate with RTL and DV block owners to debug and close gaps.

Skills

Verification planning

Regression strategy

Verification closure

Emulation workload

IP/SoC verification

SystemVerilog

C/C++

Python

Tcl

Bash

Emulation platforms

Model integration

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Palladium/Protium

Synopsys ZeBu/HAPS

Job description

At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.

Who we are

We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.

About the Role

We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to overall verification signoff. You will also develop the models and infrastructure needed to support this work.

What You’ll Do

• Verification Strategy & Planning: Translate IP and SoC verification plans into execution strategies, mapping tests to simulation, simulation acceleration, or emulator-hosted verification based on runtime, fidelity, and debug needs. Define emulation workload goals and run acceptance criteria with DV block ownersEmulation Models: Build and maintain models and test components for simulation acceleration and emulator-hosted verification flows, balancing fidelity, performance, and debug visibility.
• Emulation Infrastructure: Develop and improve platform bring-up, compile, mapping, runtime, regression, and debug flows.
  Testbench and Workload Development: Adapt or develop test environments, transactors, stimulus, and software-driven workloads that run effectively on emulation platforms.
• Emulation Closure and Signoff: Track workload execution and failures, review results with DV block owners, and help close emulation-specific gaps. Provide emulation signoff as an input to overall IP and SoC verification signoff.
• Emulation Debug and Collaboration: Triage emulation compile, runtime, and test failures; use traces, waveforms, and platform diagnostics to isolate design, model, testbench, or infrastructure issues; partner with RTL and DV block owners to resolve them.
• Agentic AI for Emulation: Build and apply agentic workflows across workload planning, model and test preparation, platform setup, run orchestration, failure triage, result analysis, and closure reporting, improving engineering throughput while keeping results traceable and reviewable by DV owners.
• Automation and Scripting: Build and maintain scripts and tools using Python, Tcl, Bash, or similar languages to improve platform usability, regression throughput, and results visibility.Skills and Qualification

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and 5+ years of industry experience.
• Hands‑on experience with platforms such as Cadence Palladium/Protium, Synopsys ZeBu/HAPS, or comparable systems, including bring‑up, model integration, compilation, execution, and debug.
• Experience building or adapting models and test environments for simulation acceleration, emulator-hosted verification, or both.
• Strong understanding of verification planning, regression strategy, and verification closure, with the ability to translate DV goals into emulation workload and run criteria.
• Experience verifying complex IP or SoCs, with an understanding of how verification needs change from block‑level to system‑level testing.
• Proficiency in SystemVerilog, C/C++, and scripting languages such as Python, Tcl, or Bash.
• Ability to assess which tests and workloads are effective on emulation platforms, including tradeoffs among runtime, fidelity, observability, and debug.
• A collaborative mindset and a bias for action when working across design, verification, software, and infrastructure teams.

Preferred Qualifications: (We encourage you to apply even if you don’t meet all of these)

• Experience using emulation for long-running software workloads, firmware and driver validation, system-level scenarios, or pre-silicon software bring‑up.
• Background developing synthesizable test components, transactors, behavioral models, or emulation-friendly replacements for simulation models.
• Experience with UVM-based verification environments and adapting them for acceleration or emulation.
• Familiarity with coverage-driven verification and SystemVerilog Assertions (SVA).Experience using emulation workloads for performance verification and power estimation.
• Experience with high-performance silicon such as CPUs, GPUs, AI accelerators, or complex SoCs.
• Experience with workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.

Logistics & Benefits

• Location: This role is based in Austin, Texas or Palo Alto, California.
• Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD, plus equity.
• Visa Sponsorship: We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
• Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.