Emulation Engineer: SoC Interconnect & Verification

Arteris; Campbell (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Arteris is seeking an Emulation Engineer to design and deliver interconnect and memory hierarchy solutions for advanced SoC designs. You will work with an expert team to create configurable, testable emulation solutions that bridge RTL and software, enabling seamless validation across mobile, automotive, and consumer domains.

You will join a proven startup environment with opportunities to influence development environments, architecture, verification, and processes, collaborating with industry

Qualifications

• 3+ years’ experience on SoC, system on chip, IPs integration or IP RTL design.
• Familiar with Verilog & SystemVerilog programming.
• Experience with emulation platforms such as Palladium, Veloce, or Zebu.
• Knowledge of ARM CHI‑E/ACE/AXI bus protocols.
• Experience of Emulator for "SoC + Software" validation.

Responsibilities

• Maintaining hardware emulation system in full operational condition
• Defining, documenting, developing and executing emulation process for multiple projects
• Integrating hardware emulation system to different software platform
• Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
• Help improve and refine emulation process, methodology, and metrics

Skills

Emulation experience

Verilog / SystemVerilog

Signal waveform debugging

Education

MS degree in EE or CS

BS degree minimum

Tools

Palladium

Veloce

Zebu

Job description

Arteris is seeking an Emulation Engineer to design and deliver interconnect and memory hierarchy solutions for advanced SoC designs. You will work with an expert team to create configurable, testable emulation solutions that bridge RTL and software, enabling seamless validation across mobile, automotive, and consumer domains.

You will join a proven startup environment with opportunities to influence development environments, architecture, verification, and processes, collaborating with industry