Emulation Engineer, SoC Interconnect & Verification

Arteris; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Arteris is seeking an Emulation Engineer in the San Jose area to design and deliver interconnect and memory hierarchy solutions for mobile, telecom, automotive, and consumer SoC designs. You will work with RTL and software to provide configurable, testable, high-quality emulation outcomes and influence development environments and verification processes.

Ideal candidates have 3+ years on SoC/IP integration, strong Verilog/SystemVerilog skills, and hands-on experience with emulation platforms

Qualifications

• 3+ years’ experience on SoC, system on chip, IPs integration or IP RTL design; familiarity with Verilog & SystemVerilog.
• Strong emulation experience on platforms such as Palladium, Veloce, or Zebu; including compilation, debug, performance, and throughput optimization.
• Knowledge of ARM CHI-E/ACE/AXI bus protocols.
• Experience of Emulator for 'SoC + Software' validation; Siemens Veloce experience is a plus.
• Strong skill on signal waveform debugging using visualization tools.

Responsibilities

• Maintain hardware emulation system in full operational condition.
• Define, document, develop and execute emulation processes for multiple projects.
• Integrate hardware emulation system with different software platforms.
• Triaging regressions and debugging RTL designs in Verilog and SystemVerilog.
• Improve and refine emulation processes, methodologies, and metrics.

Skills

Verilog

SystemVerilog

Emulation

SoC/IP integration

Debug signal waveforms

Education

MS degree in EE/CS

BS degree minimum

Tools

Palladium

Veloce

Zebu

Job description

Arteris is seeking an Emulation Engineer in the San Jose area to design and deliver interconnect and memory hierarchy solutions for mobile, telecom, automotive, and consumer SoC designs. You will work with RTL and software to provide configurable, testable, high-quality emulation outcomes and influence development environments and verification processes.

Ideal candidates have 3+ years on SoC/IP integration, strong Verilog/SystemVerilog skills, and hands-on experience with emulation platforms