Edge AI Hardware PM: NPU-Chiplet & SoC Roadmap

NXP Semiconductors; Northern (KY); Hybrid; USD 180.000 - 260.000; Vollzeit

Zusammenfassung

NXP Semiconductors seeks a senior hardware product manager to lead the NPU and IP roadmap across Ara-series NPUs, i.MX IP, and chiplet-scale architectures. You will translate customer needs into silicon specs, drive architecture tradeoffs, and own the business case including BOM, ASP, and margins.

You will partner with i.MX, S32 SoC, i.MCU, and RT teams to define integration requirements, lead make/buy/IP-license decisions, and shape competitive strategy for NPU silicon.

Qualifikationen

• 10+ years of product management or product strategy experience in semiconductor or silicon IP.
• Experience defining silicon product specifications — performance targets, memory architecture, power envelopes, packaging, and process node decisions.
• Strong understanding of SoC and IP integration — experience defining IP for integration into a host processor or SoC.
• Familiarity with chiplet architectures and multi-chip interconnect standards (UCIe, BoW, or equivalent).
• Track record of driving design wins and customer adoption across multiple product generations.
• Ability to build and defend business cases including BOM cost, ASP, gross margin, and market sizing.
• Experience with competitive analysis and differentiation strategy in a fast-moving semiconductor segment.
• Strong cross-functional leadership skills — drive alignment across architecture, engineering, sales, marketing, and executives.
• Excellent written and verbal communication skills; able to present complex tradeoffs to engineers and executives.

Aufgaben

• Define and maintain the multi-generational hardware roadmap across NPUs (Ara series), i.MX-integrated NPU IP, and chiplet-based scale-out architectures.
• Translate customer requirements and competitive intelligence into silicon product specifications including performance targets and architecture decisions.
• Drive product definition through architecture reviews, design partitioning, and feature tradeoffs with silicon architects and engineering leads.
• Own the business case for each hardware product — BOM cost, ASP, gross margin targets, volumes, and NPV — and present investment recommendations to executives.
• Lead make-vs-buy-vs-IP-license assessments for new capabilities including MAC array architectures and multi-chip interconnects.
• Define chiplet strategy for scale-out NPU configurations — die partitioning, die-to-die interfaces, and multi-chip package requirements.
• Partner with i.MX, S32 SoC, i.MCU, and RT product teams to define integration requirements — power domains, interfaces, memory bandwidth, and SoC bring-up.
• Drive early access and customer sampling; gather validated requirements to inform architecture decisions.
• Own the competitive benchmarking framework — track NPU silicon from major vendors; define differentiation on form factors, performance, power, cost, and software ecosystem.
• Manage lifecycle from definition through ramp, sustaining, and EOL; include customer transitions across generations.
• Represent the NPU hardware portfolio to executives, customers, partners, and at industry events.
• Co-own SW development of dNPU and chiplet-based designs with the SW product manager.
• Develop end-to-end system solutions and demonstration platforms for hardware/software developers at industry events and conferences.

Kenntnisse

Product management

Hardware roadmap

SoC/IP integration

Cross-functional leadership

Competitive analysis

Executive communication

Business case development

Ausbildung

MBA or advanced degree in Electrical/Computer Engineering

Jobbeschreibung

NXP Semiconductors seeks a senior hardware product manager to lead the NPU and IP roadmap across Ara-series NPUs, i.MX IP, and chiplet-scale architectures. You will translate customer needs into silicon specs, drive architecture tradeoffs, and own the business case including BOM, ASP, and margins.

You will partner with i.MX, S32 SoC, i.MCU, and RT teams to define integration requirements, lead make/buy/IP-license decisions, and shape competitive strategy for NPU silicon.