Edge & Physical AI HW Product Manager/Director

NXP Semiconductors; Arizona; On-site; USD 180,000 - 260,000; Full time

Job summary

NXP Semiconductors seeks a senior hardware product manager to lead the NPU and IP roadmap across Ara-series NPUs, i.MX IP, and chiplet-scale architectures. You will translate customer needs into silicon specs, drive architecture tradeoffs, and own the business case including BOM, ASP, and margins.

You will partner with i.MX, S32 SoC, i.MCU, and RT teams to define integration requirements, lead make/buy/IP-license decisions, and shape competitive strategy for NPU silicon.

Qualifications

• 10+ years of product management or product strategy experience in semiconductor or silicon IP.
• Experience defining silicon product specifications — performance targets, memory architecture, power envelopes, packaging, and process node decisions.
• Strong understanding of SoC and IP integration — experience defining IP for integration into a host processor or SoC.
• Familiarity with chiplet architectures and multi-chip interconnect standards (UCIe, BoW, or equivalent).
• Track record of driving design wins and customer adoption across multiple product generations.
• Ability to build and defend business cases including BOM cost, ASP, gross margin, and market sizing.
• Experience with competitive analysis and differentiation strategy in a fast-moving semiconductor segment.
• Strong cross-functional leadership skills — drive alignment across architecture, engineering, sales, marketing, and executives.
• Excellent written and verbal communication skills; able to present complex tradeoffs to engineers and executives.

Responsibilities

• Define and maintain the multi-generational hardware roadmap across NPUs (Ara series), i.MX-integrated NPU IP, and chiplet-based scale-out architectures.
• Translate customer requirements and competitive intelligence into silicon product specifications including performance targets and architecture decisions.
• Drive product definition through architecture reviews, design partitioning, and feature tradeoffs with silicon architects and engineering leads.
• Own the business case for each hardware product — BOM cost, ASP, gross margin targets, volumes, and NPV — and present investment recommendations to executives.
• Lead make-vs-buy-vs-IP-license assessments for new capabilities including MAC array architectures and multi-chip interconnects.
• Define chiplet strategy for scale-out NPU configurations — die partitioning, die-to-die interfaces, and multi-chip package requirements.
• Partner with i.MX, S32 SoC, i.MCU, and RT product teams to define integration requirements — power domains, interfaces, memory bandwidth, and SoC bring-up.
• Drive early access and customer sampling; gather validated requirements to inform architecture decisions.
• Own the competitive benchmarking framework — track NPU silicon from major vendors; define differentiation on form factors, performance, power, cost, and software ecosystem.
• Manage lifecycle from definition through ramp, sustaining, and EOL; include customer transitions across generations.
• Represent the NPU hardware portfolio to executives, customers, partners, and at industry events.
• Co-own SW development of dNPU and chiplet-based designs with the SW product manager.
• Develop end-to-end system solutions and demonstration platforms for hardware/software developers at industry events and conferences.

Skills

Product management

Hardware roadmap

SoC/IP integration

Cross-functional leadership

Competitive analysis

Executive communication

Business case development

Education

MBA or advanced degree in Electrical/Computer Engineering

Job description

**Job Responsibilities:*** Define and maintain the multi-generational hardware roadmap across discrete NPUs (Ara series), i.MX-integrated NPU IP, and chiplet-based scale-out architectures* Translate customer requirements and competitive intelligence into silicon product specifications including performance targets (TOPS, TOPS/W, TOPS/sq.mm), memory architecture, power, I/O, packaging, safety and process node decisions* Drive product definition through architecture review, design partitioning, and feature tradeoff decisions in close collaboration with silicon architects and engineering leads* Own the business case for each hardware product — BOM cost, ASP, gross margin targets, volume projections, and NPV — and present investment recommendations to executive leadership* Lead make-vs-buy-vs-IP-license assessments for new capabilities including MAC array architectures like in-memory compute, non-uniform memory subsystems, memory architectures and interconnect IP like UCIe* Define chiplet strategy for scale-out NPU configurations — including die partitioning, die-to-die interface selection, and multi-chip package requirements to support larger model inference workloads* Partner with the i.MX, S32 SoC, i.MCU, and RT product teams to define NPU IP integration requirements, including power domains, bus interfaces, memory bandwidth allocation, software-hardware co-design constraints, SoC bring-up, and debugging.* Drive early access and customer sampling programs; gather validated product requirements from lead customers and feed them into architecture decisions before freeze* Own the competitive benchmarking framework — track competing NPU silicon from Qualcomm, Nvidia, RockChip, Hailo, Axelera, Ambarella, and others; define differentiation strategy on formfactors, performance, power, cost, safety, support and software ecosystem* Manage product lifecycle from definition through ramp, sustaining, and EOL — including customer transition plans across generations* Represent the NPU hardware portfolio to NXP executive leadership, customers, partners, and at industry events* Co-own SW development of dNPU, integrated and chiplet based designs w/ the SW product manager* Develop end-to-end system solutions and demonstration platforms for hardware and software developers at industry events and conferences.**Job Qualifications:*** 10+ years of product management or product strategy experience in semiconductor or silicon IP, with direct ownership of hardware product definition and roadmap* Hands-on experience defining silicon product specifications — performance targets, memory architecture, power envelopes, packaging, and process node decisions* Strong understanding of SoC and IP integration — experience defining IP for integration into a host processor or SoC is strongly preferred* Familiarity with chiplet architectures and multi-chip interconnect standards (UCIe, BoW, or equivalent) is a significant plus* Track record of driving design wins and customer adoption across multiple product generations* Ability to build and defend business cases including BOM cost, ASP, gross margin, and market sizing* Experience with competitive analysis and differentiation strategy in a fast-moving semiconductor segment* Strong cross-functional leadership skills — ability to drive alignment across architecture, engineering, sales, marketing, and executive stakeholders* Excellent written and verbal communication skills; able to represent complex technical tradeoffs to both engineering teams and executive audiences**Good to have:*** Direct experience in AI/ML inference silicon — NPU, GPU, or inference accelerator product management* Familiarity with inference workloads including CNNs, transformers, LLMs, and VLM variants deployed at the edge* Experience working with ODMs, OEMs, and contract manufacturers on board design, system integration, and production* Background in industrial, automotive, or embedded edge markets* MBA or advanced degree in Electrical Engineering, Computer Engineering, or related discipline