ECC Design Intern: FPGA/Verilog, RTL (Onsite)

SK hynix memory solutions America Inc.; San Jose (CA); On-site; USD 34,440,000 - 48,216,000; Full time

Job summary

SK Hynix Memory Solution is seeking a motivated intern to contribute to SK Start-of-Art ECC IPs, a core part of ESSD. You will work on FPGA systems, collect performance data, and support ongoing development in a fast-paced team.

The internship is 40 hours per week for 6 months, onsite in San Jose, with immediate start (Sept/Oct 2026). You will code RTL in Verilog/SystemVerilog, run simulations with VCS, and collaborate with designers and verification engineers to deliver correct solutions.

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.
• Proficiency in Verilog/SystemVerilog.
• Available to work 40 hours per week.
• 100% onsite for a 6 months duration.

Responsibilities

• Work on FPGA system performance data collection.
• Code RTL in Verilog/SystemVerilog.
• Run simulations with Synopsys VCS.
• Debug simulation environment and tool issues.
• Collaborate with designers and verification engineers for solutions.

Skills

Lab skills

Communication

Punctuality

Education

BS/MS in EE/CE or related

Tools

Verilog

SystemVerilog

Job description

SK Hynix Memory Solution is seeking a motivated intern to contribute to SK Start-of-Art ECC IPs, a core part of ESSD. You will work on FPGA systems, collect performance data, and support ongoing development in a fast-paced team.

The internship is 40 hours per week for 6 months, onsite in San Jose, with immediate start (Sept/Oct 2026). You will code RTL in Verilog/SystemVerilog, run simulations with VCS, and collaborate with designers and verification engineers to deliver correct solutions.