Design Verification Engineer Intern - SoC/Memory

SK hynix memory solutions America Inc.; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Job summary

SK Hynix Memory Solution is seeking an engineering intern in San Jose for a 6‑month program with a 40‑hour work week starting September or October 2026. The role focuses on microarchitecture study of SOC TOP, verification planning, and test bench enhancements.

The candidate should hold a BSEE/MSEE or related degree and have experience in digital IC design, SystemVerilog/UVM, Python/Perl, and working in Windows/Linux environments. Familiarity with Perforce/Confluence is a plus.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or a related field is required.
• Digital IC Design & Verification experiences.
• Work in Windows and Linux environment.
• Python or Perl scripting experience.
• Experience in System Verilog, UVM, C/Assembly coding
• Experience in Perforce and Confluence.
• Familiarity with UCIe, CPU architecture, NAND protocols, and AI productivity tools is a plus.

Responsibilities

• Study the Microarchitecture of the Design (SOC TOP) and list the Verification Requirements for testing.
• Modify the Test Bench for the SOC TOP level testing.
• Create/Modify Tests Cases to test the functionalities of the SOC.
• Debug & identify the issue & file bug reports to Designer.
• Testing to meet the Coverages (Functional, Toggle) criteria.

Job description

SK Hynix Memory Solution is seeking an engineering intern in San Jose for a 6‑month program with a 40‑hour work week starting September or October 2026. The role focuses on microarchitecture study of SOC TOP, verification planning, and test bench enhancements.

The candidate should hold a BSEE/MSEE or related degree and have experience in digital IC design, SystemVerilog/UVM, Python/Perl, and working in Windows/Linux environments. Familiarity with Perforce/Confluence is a plus.