Memory Design Verification Engineer Intern

SK hynix memory solutions; San Jose (CA); On-site; USD 73,000 - 94,000; Full time

Job summary

SK hynix memory solutions in San Jose is offering a 6-month internship. You will study the microarchitecture of the Design (SOC TOP), modify the Test Bench for SOC TOP level testing, and create/test cases to verify functionality. Start date is immediate (Sept/Oct 2026).

Minimum requirements include a BSEE/MSEE or related field, Windows and Linux experience, and scripting in Python or Perl. Proficiency in System Verilog/UVM, C/Assembly, and familiarity with Perforce and Confluence are valued.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or a related field is required.
• Experience working in Windows and Linux environments.
• Scripting experience in Python or Perl.

Responsibilities

• Study the Microarchitecture of the Design (SOC TOP) and list the Verification Requirements for testing.
• Modify the Test Bench for the SOC TOP level testing.
• Create/Modify Tests Cases to test the functionalities of the SOC.
• Debug & identify the issue & file bug reports to Designer.
• Testing to meet the Coverages (Functional, Toggle) criteria.

Job description

SK hynix memory solutions in San Jose is offering a 6-month internship. You will study the microarchitecture of the Design (SOC TOP), modify the Test Bench for SOC TOP level testing, and create/test cases to verify functionality. Start date is immediate (Sept/Oct 2026).

Minimum requirements include a BSEE/MSEE or related field, Windows and Linux experience, and scripting in Python or Perl. Proficiency in System Verilog/UVM, C/Assembly, and familiarity with Perforce and Confluence are valued.