Design Verification Engineer Intern — SOC TOP

SKHMS Corporation; San Jose (CA); Hybrid; USD 48,000 - 62,000; Full time

Benefits offered by this job

6-month internship

Job summary

SK hynix memory solutions America Inc. is seeking an enthusiastic engineering intern for a 6-month program in San Jose. The role focuses on microarchitecture study, SOC TOP verification, and test bench work in Windows and Linux.

Start date is immediate (Sept 2026/Oct 2026) with 40 hours per week and compensation ranging from $35 to $45 per hour. Candidates should have a BSEE/MSEE or related field, plus Python/Perl scripting and SystemVerilog/UVM experience.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or related field.
• Experience with Windows and Linux environments.
• Scripting in Python or Perl.
• Experience with SystemVerilog, UVM, C/Assembly.
• Experience with Perforce and Confluence.
• Familiarity with UCIe, CPU architecture, NAND protocols; AI productivity tools is a plus.

Responsibilities

• Study the microarchitecture of the Design (SOC TOP) and list verification requirements for testing.
• Modify the Test Bench for the SOC TOP level testing.
• Create/Modify test cases to test SOC functionalities.
• Debug and identify issues, file bug reports to the designer.
• Test to meet Functional and Toggle coverage criteria.

Skills

Python scripting

Perl scripting

Windows OS

Linux OS

Education

Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or related field

Tools

SystemVerilog

UVM

C/Assembly

Perforce

Confluence

UCIe knowledge

CPU architecture

NAND protocols

AI productivity tools

Job description

SK hynix memory solutions America Inc. is seeking an enthusiastic engineering intern for a 6-month program in San Jose. The role focuses on microarchitecture study, SOC TOP verification, and test bench work in Windows and Linux.

Start date is immediate (Sept 2026/Oct 2026) with 40 hours per week and compensation ranging from $35 to $45 per hour. Candidates should have a BSEE/MSEE or related field, plus Python/Perl scripting and SystemVerilog/UVM experience.