Senior Power & Limits Architect for High-Performance SoCs

Qualcomm; San Diego (CA); On-site; USD 174,000 - 262,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an experienced ASIC Engineer to define, model, and implement power and limits IP across high-performance devices. You will verify and document implementations, collaborating with cross-functional teams to meet thermal and power goals.

The role emphasizes deep knowledge of power delivery, DCVS, and system interactions to sustain CPU/GPU performance while managing temperature and power constraints.

Qualifications

• Minimum qualifications: with Bachelor's: 6+ years ASIC design/verification; with Master's: 5+ years; with PhD: 4+ years.
• Candidate will develop power and limits system to maximize performance within thermal/power envelopes.
• Strong experience with UPF, power domains, and cross-domain interactions.

Responsibilities

• Define, model, design, verify and document IP/SoC power and limits architectures.
• Work across system, software, and product teams to optimize power delivery and performance.

Skills

Power and limits system

UPF

Low power design

Clock domain crossing

Perl

Python scripting

Post-Si debug

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Perl

Python

Job description

Qualcomm Technologies, Inc. seeks an experienced ASIC Engineer to define, model, and implement power and limits IP across high-performance devices. You will verify and document implementations, collaborating with cross-functional teams to meet thermal and power goals.

The role emphasizes deep knowledge of power delivery, DCVS, and system interactions to sustain CPU/GPU performance while managing temperature and power constraints.