Power & Thermal Architect for Data Center SoCs

Qualcomm; San Diego (CA); On-site; USD 164,000 - 264,500; Full time

Benefits offered by this job

Annual bonus program

RSU grants

Competitive benefits package

Job summary

Qualcomm Technologies, Inc. in San Diego seeks a Data Center Power & Limits Architect to define and drive next-generation power management, thermal, and system limits architecture for large-scale compute platforms.

You will enable maximum sustained performance within constrained power, cooling, and reliability envelopes across silicon, platform, and data center infrastructure. The role covers dynamic power control systems, telemetry interfaces, cross-layer co-design, and modeling/validation

Qualifications

• 10+ years of experience in power or system architecture.
• Deep expertise in power management systems and limits control.
• Strong understanding of data center/server architectures and PDN.
• Experience with modeling/analysis tools (MATLAB, Python).

Responsibilities

• Define holistic power, thermal, and limits architecture across silicon to data center.
• Design power budgeting, allocation, and enforcement across CPUs/GPUs/memory.
• Develop dynamic power control and telemetry-driven optimization.
• Model, simulate, and validate architectures using MATLAB/Simulink.
• Collaborate cross-layer with silicon, platform, software, and data center teams.
• Drive innovations for AI/HPC workloads within constrained infrastructure.

Skills

Power management

DVFS/DCVS

Thermal management

Control systems

Telemetry

Data center architecture

MATLAB

Python

Education

Bachelor's degree in Science or Engineering

Master's degree in Science or Engineering

PhD in Science or Engineering

Tools

MATLAB

Python

Job description

Qualcomm Technologies, Inc. in San Diego seeks a Data Center Power & Limits Architect to define and drive next-generation power management, thermal, and system limits architecture for large-scale compute platforms.

You will enable maximum sustained performance within constrained power, cooling, and reliability envelopes across silicon, platform, and data center infrastructure. The role covers dynamic power control systems, telemetry interfaces, cross-layer co-design, and modeling/validation