DSP Core Architect & RTL Engineer - Hexagon

QUALCOMM, Inc.; Austin (TX); On-site; USD 160,000 - 240,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a motivated engineer to contribute to the development of high‑performance, energy‑efficient CPU cores within the Hexagon team.

You will own microarchitecture and RTL development, tackling low‑power optimization, performance exploration, and timing challenges in a collaborative environment. The role focuses on areas like processor pipelines, out-of-order execution, caches, memory hierarchy, and multi‑processor systems.

Qualifications

• 1–12 years of experience in CPU architecture and RTL design.
• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 3+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• 2+ years of experience with high-performance microprocessor design.

Responsibilities

• Own microarchitecture and RTL development, including low-power optimizations, performance exploration, and achieving area and timing goals.
• Collaborate with cross‑functional teams to meet project milestones and quality targets.

Skills

CPU architecture

RTL design

Microprocessor design

Education

Bachelor’s degree in EE/CS/CE

Master’s degree in EE/CS/CE

PhD in EE/CS/CE

Tools

RISC-V

Job description

Qualcomm Technologies, Inc. is seeking a motivated engineer to contribute to the development of high‑performance, energy‑efficient CPU cores within the Hexagon team.

You will own microarchitecture and RTL development, tackling low‑power optimization, performance exploration, and timing challenges in a collaborative environment. The role focuses on areas like processor pipelines, out-of-order execution, caches, memory hierarchy, and multi‑processor systems.