DRAM Power Architect - Shape Energy-Efficient Memory

Micron Technology; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical plan

Paid time off

Retirement benefits

Job summary

Micron Technology is seeking a DRAM Power Modeling Engineer to define and optimize power behavior from device to system level. You will collaborate with architecture, design, product, and system teams to analyze power consumption, build models, and influence decisions for better performance and efficiency.

The role emphasizes translating data into actionable insights and working across teams to drive memory technology improvements.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Experience with semiconductor memory or system architecture analysis.
• Knowledge of DRAM operation and power consumption.
• Experience with data analysis, modeling, or tool development.

Responsibilities

• Analyze system- and customer-level DRAM power requirements and translate to power modeling.
• Perform DRAM power analysis, IDD characterization, and workload-based modeling.
• Develop and apply power models, methodologies, and tools.
• Support power target definition and feature evaluation balancing power, performance, efficiency.
• Collaborate with cross-functional teams to validate results and communicate findings.

Skills

Power modeling

DRAM architecture analysis

Data analysis

Cross-functional communication

Engineering tools

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Micron Technology is seeking a DRAM Power Modeling Engineer to define and optimize power behavior from device to system level. You will collaborate with architecture, design, product, and system teams to analyze power consumption, build models, and influence decisions for better performance and efficiency.

The role emphasizes translating data into actionable insights and working across teams to drive memory technology improvements.