DRAM Power Architect: Shape Efficient Memory Futures

Micron Technology, Inc; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. seeks a DRAM Power Architect (MTS) to define and optimize DRAM power behavior from device to system level. You will analyze power consumption, develop models, and influence design decisions with architecture, design, product, and system teams.

The role emphasizes analytical thinking, data-driven insights, and collaboration to improve performance and efficiency across memory solutions.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience with semiconductor, memory, or system architecture analysis.
• Knowledge of DRAM operation, power consumption mechanisms, and performance tradeoffs.
• Experience with data analysis, modeling, simulation, or tool development for engineering applications.
• Ability to communicate technical concepts and findings effectively across engineering teams.

Responsibilities

• Analyze system- and customer-level DRAM power requirements and translate them into power modeling and evaluation activities
• Perform DRAM power analysis, including IDD characterization and workload-based modeling, to identify optimization opportunities
• Develop and apply power models, methodologies, and tools to assess DRAM architecture and system behavior
• Support power target definition and feature evaluation to balance power, performance, and efficiency objectives
• Collaborate with cross-functional teams to validate results, benchmark competitive products, and communicate technical findings

Skills

Data analysis

Power modeling

Simulation

Engineering tools development

Communication

Education

Bachelor’s degree in Electrical/Computer Engineering, CS

Experience in semiconductor/memory architecture analysis

Job description

Micron Technology, Inc. seeks a DRAM Power Architect (MTS) to define and optimize DRAM power behavior from device to system level. You will analyze power consumption, develop models, and influence design decisions with architecture, design, product, and system teams.

The role emphasizes analytical thinking, data-driven insights, and collaboration to improve performance and efficiency across memory solutions.