DRAM Power Architect — Modeling & Optimization

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking an engineer to define and optimize DRAM power behavior from device to system levels.

You will work with architecture, design, product, and system teams to analyze power consumption, build models, and influence decisions that improve performance and efficiency. The role emphasizes data-driven analysis, modeling, and tool development to support power targets and feature evaluations across multiple DRAM platforms.

Qualifications

• Experience with semiconductor, memory, or system architecture analysis.
• Knowledge of DRAM operation, power consumption, and performance tradeoffs.
• Experience with data analysis, modeling, simulation, or tool development for engineering applications.
• Ability to communicate technical concepts across engineering teams.

Responsibilities

• Analyze system- and customer-level DRAM power requirements and translate to power modeling.
• Perform DRAM power analysis, including IDD characterization and workload-based modeling.
• Develop and apply power models, methodologies, and tools.
• Support power target definition and feature evaluation balancing power, performance, and efficiency.
• Collaborate with cross-functional teams to validate results and communicate findings.

Skills

Data analysis

Modeling

Simulation

Tool development

Communication

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master’s or PhD preferred

Job description

Micron Technology, Inc. is seeking an engineer to define and optimize DRAM power behavior from device to system levels.

You will work with architecture, design, product, and system teams to analyze power consumption, build models, and influence decisions that improve performance and efficiency. The role emphasizes data-driven analysis, modeling, and tool development to support power targets and feature evaluations across multiple DRAM platforms.