DFT Engineer

engineeringjobs.net, Inc.; United States; On-site; USD 110,000 - 190,000; Full time

Job summary

engineeringjobs.net, Inc. is seeking an experienced Tests and Debug Integration Engineer to design and implement DFT/DFD tech for cutting-edge APU and GPU products. You will deploy test and debug solutions to local end-users, train teams, and ensure projects meet schedule, quality, and cost targets.

You will develop integration plans, provide ongoing support for RTL and verification flows, and collaborate with Central-DFX to drive improvements and successful silicon bring-up and failure analysis.

Qualifications

• 3 to 10 years of complex semiconductor design experience.
• Direct knowledge of the Verilog language, pre-silicon simulators, and waveform debugging tools.
• Proficiency in debugging both RTL and gate level simulations.
• Familiarity with design tools: synthesis, logic equivalency and static timing.
• Experience in semi-conductor technologies including: JTAG/IEEE standards, scan/ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
• Good knowledge of UNIX/Linux and scripting languages (such as: TCL, c-shell, Perl, Ruby or Python scripts) and software writing skills.
• Exceptional: Knowledge of ATE and digital IC manufacturing test.
• Exceptional: Solving logic design or timing issues with integration, synthesis and PD teams.

Responsibilities

• Deploy test-related and debug-related technology to local end-users, including training and hands-on aid during bring-up.
• Develop and execute integration plans; communicate status.
• Support local end-users with flow deployment and RTL/verification integration.
• Collect feedback and suggest improvements to Central-DFX team.
• Provide bring-up support during first Silicon bring-up, qualification and failure analysis.

Skills

Communication

Independence

Problem solving

Travel

Tools

Verilog

Waveform debugging tools

Synthesis

Static timing

Job description

This openings is with one of our client - Product based MNC

The team is responsible for design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) technology for complex state-of-the-art APU computing and GPU graphics products. The technology is used by all of AMD's SOC and IP teams. We thrive on constant innovation and we strive to be the leaders in DFT and DFD.

TEST AND DEBUG INTEGRATION ENGINEERING RESPONSIBILITIES

• Deploy test-related and debug-related technology to local end-users (includes training, hands-on aid during bring-up and beyond, technology qualification and on-site scripting to ensure that projects execute with the best schedules, quality and cost)
• Develop and execute integration plans; communicate status
• Support local end-users as needed:
  • Flow deployment
  • RTL and verification technology integration/deployment
  • RTL integration, synthesis, equivalence checks, and timing
  • Special purpose software support
• Collect feedback and suggest improvements to rest of Central-DFX team
• Provide bring-up support to Product and Platform Engineering teams during first Silicon bring-up, qualification and failure analysis

WORK STYLE

• Strong communication skills in English (verbal and written)
• Willingness and initiative to ensure project success and drive improvement
• Willing to travel for extended training or support
• Confident and able to work independently
• Strong problem solving skills in software and SOC/ASIC design

EXPERIENCE AND KNOWLEDGE

• - 3 to 10 years of complex semiconductor design experience
• Direct knowledge of the Verilog language, pre-silicon simulators, and waveform debugging tools
• Proficiency in debugging both RTL and gate level simulations
• Familiarity with design tools: synthesis, logic equivalency and static timing
• Experience in semi-conductor technologies including: JTAG/IEEE standards, scan/ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
• Good knowledge of UNIX/Linux and scripting languages (such as: TCL, c-shell, Perl, Ruby or Python scripts) and software writing skills
• Exceptional: Knowledge of ATE and digital IC manufacturing test
• Exceptional: Solving logic design or timing issues with integration, synthesis and PD teams