DPU Power Architect, Infrastructure Silicon

Meta; Sunnyvale (CA); Presencial; USD 180.000 - 240.000; Jornada completa

Descripción de la vacante

Meta is seeking an experienced Power Architect for Infrastructure Silicon in Sunnyvale to drive power modeling, analysis, and architectural power optimization of DPUs. You will influence architecture decisions from early design through RTL/gate-level power analysis and silicon correlation to deliver leading performance-per-watt on data center workloads.

The role focuses on building system-level power models, identifying bottlenecks, and implementing DVFS, power gating, and other power-saving

Formación

• Experience creating workload-driven power models for architectural analysis.
• Ability to abstract power-relevant behaviors from real workloads.
• Experience building system-level power models and tracking estimates through RTL/gate-level power.

Responsabilidades

• Analyze real-world DPU software use cases to identify power bottlenecks.
• Build and maintain workload-driven power models and rollups across architectures.
• Quantify trade-offs in PPA, focusing on energy-per-transaction and performance-per-watt.
• Define and drive power-saving features like DVFS, power gating, and clock gating.
• Analyze SoC pipelines and data movement to optimize power vs performance.
• Own power budgets and provide inputs to power delivery and thermal teams.
• Correlate pre-silicon projections with post-silicon measurements and improve methods.

Conocimientos

Power modelling

Workload analysis

System-level models

RTL power analysis

DVFS / power-saving

Educación

Bachelor's degree in Computer Science/Engineering or related field

Descripción del empleo

Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We are seeking an experienced Power Architect to drive power modeling, analysis, and architectural power optimization of our Data Processing Unit (DPU) designs. In this role you will influence architecture and microarchitecture decisions from early path-finding through RTL/gate-level power analysis and silicon correlation, ensuring our DPUs deliver leading performance-per-watt on real data center workloads.

DPU Power Architect, Infrastructure Silicon Responsibilities:

• Analyze and characterize real-world DPU software use cases (network virtualization, storage offload, crypto/compression, packet processing) to identify hardware power bottlenecks and power-relevant behaviors
• Build and maintain workload-driven, system-level power models and power rollups for current and future SmartNIC/IPU/DPU architectures, tracking accuracy from early analytical estimates through RTL and gate-level power analysis
• Quantify architectural and micro-architectural trade-offs with respect to PPA, with emphasis on energy-per-transaction, power-per-bit moved, and performance-per-watt, to inform and guide design decisions
• Define and drive structural power-saving architecture features, including DVFS, AVS, power gating, clock gating, activity throttling, power state management, and workload-aware power policies
• Analyze SoC pipelines and data movement paths (host-to-DPU, memory/fabric/network traffic) to understand and optimize the power-versus-performance trade-off
• Own power budgets and provide power-delivery and thermal inputs in partnership with design, physical design, firmware, platform, and software teams
• Correlate pre-silicon power projections with post-silicon measurements and drive methodology improvements based on findings

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Experience in workload analysis and characterization, and abstracting power-relevant behaviors into models for architectural analysis
• Experience building system-level power models and power rollups, and tracking them from early estimates through RTL/gate-level power
• Experience defining or evaluating architectural power-saving features such as DVFS, power gating, and clock gating
• Understanding of SoC pipelines and how data movement impacts power versus performance