ASIC Power Management Architect

Anysilicon; Mountain View (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Google is seeking an experienced hardware-focused engineer to advance custom silicon initiatives in Mountain View. You will drive architectural analysis of mempath traffic, collect silicon traffic patterns, and map them to pre-silicon CUJ estimates to shape power- and performance-oriented decisions.

You will oversee end-to-end correlation from pre-silicon power estimates to CUJ modeling, propose features to improve KPIs, and conduct algorithm development and modeling across various architecture

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience.
• Master's degree or PhD preferred in related field.

Responsibilities

• Drive architectural analysis for mempath traffic patterns and map to pre-silicon CUJ estimates.
• Oversee correlation from pre-silicon power estimates to CUJ modeling estimates for architectural assumptions.
• Propose architectural features for mempath to enhance KPIs.
• Perform algorithm development, modeling, and analysis of architecture approaches.

Skills

ASIC power management architecture

Power modeling

DVFS/AVS

Hardware/software power control flows

Virtual prototyping

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science (preferred)

Tools

TLM environments

Virtual prototyping

Job description

Join Google's innovative team focused on developing custom silicon solutions that enhance the performance of direct-to-consumer products. This role offers the opportunity to shape the future of hardware experiences, contributing to technology that improves lives globally.

Responsibilities:

• Drive architectural analysis for mempath traffic patterns, collecting silicon traffic patterns for key tensor CUJs and mapping them to pre-silicon CUJ estimates.
• Oversee end-to-end correlation from pre-silicon micro benchmark power estimates to CUJ modeling estimates, focusing on architectural assumptions used for modeling.
• Propose architectural features and requirements for mempath to enhance overall Key Performance Indicators (KPIs).
• Perform algorithm development, modeling, and analysis of various architecture approaches.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with ASIC power management architecture.
• Experience with hardware or software power control flows and methodology.

Skills:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture (preferred).
• Experience with power components, power modeling, and power management techniques such as Voltage Frequency Scaling (DVFS/AVS).
• Experience modeling and validating in virtual prototyping and TLM environments.
• Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system.