Chief Memory Architect & Engineering Leader

Western Digital Corporation; San Jose (CA); On-site; USD 243,000 - 324,000; Full time

Job summary

Western Digital Corporation in San Jose is seeking the most senior technical contributor in memory design to own end-to-end architecture from concept through silicon qualification. You will arbitrate power, performance and area trade-offs and serve as the final technical authority across design, process and product engineering.

Define memory subsystem architecture, drive floorplan, own multi-generation roadmaps, and decide cross-functional trade-offs.

Qualifications

• MS/PhD in EE, CE or related field.
• 15+ years in memory or mixed-signal IC development; 5+ as architect or chief engineer.
• 2+ memory products owned from architecture through production silicon.
• Deep advanced CMOS FinFET expertise: layout, variability, reliability, DFM.
• Memory architecture breadth (DRAM, NAND/NOR, SRAM, emerging NVM), depth in one.
• Modern Cadence/Synopsys custom and digital flows through full-chip sign-off.
• Owned EDA/CAD strategy; led multi-site programs through influence.

Responsibilities

• Define the memory subsystem architecture (array, periphery, I/O, redundancy, test, reliability) and turn product requirements into a design spec.
• Drive floorplan and physical architecture: array efficiency, periphery partitioning, power delivery, die-level signal integrity.
• Own the multi-generation roadmap: node migration, density and performance scaling.
• Decide cross-functional trade-offs across process integration, circuits, DFT, packaging and controller/firmware interfaces.
• Own design methodology and EDA/CAD strategy: tools, flows, vendors, licenses.
• Mentor senior and principal engineers through architecture and design reviews.
• Represent the architecture to executives, customers, foundry partners and standards bodies.

Skills

Memory architecture

CMOS FinFET

EDA strategy

Architecture leadership

Sign-off flows

Education

MS/PhD in EE or related field

Tools

Cadence

Synopsys

Full-chip sign-off

Job description

Western Digital Corporation in San Jose is seeking the most senior technical contributor in memory design to own end-to-end architecture from concept through silicon qualification. You will arbitrate power, performance and area trade-offs and serve as the final technical authority across design, process and product engineering.

Define memory subsystem architecture, drive floorplan, own multi-generation roadmaps, and decide cross-functional trade-offs.