Digital Design Verification Engineer Mixed

Talent 101, Inc; Tucson (AZ); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

Talent 101 is seeking an experienced Digital Design Verification Engineer to support mixed-signal semiconductor devices where small digital blocks operate with analog circuitry. The role requires strong SystemVerilog verification experience and the ability to interpret incomplete requirements through collaboration with analog designers.

You will develop verification plans, maintain the DV environment, and run regressions across RTL and gate-level simulations.

Qualifications

• Hands-on digital design verification experience for ASIC, mixed-signal IC, or semiconductor designs.
• Strong SystemVerilog verification experience.
• Ability to learn and modify an existing verification environment.

Responsabilités

• Learn and understand an existing SystemVerilog-based digital verification environment and its architecture.
• Review and execute test cases from previous projects.
• Develop a comprehensive testcase list and verification plan for the new device.
• Implement, debug, and maintain the SystemVerilog verification testcase suite.
• Verify small digital blocks used for test-mode communication, memory programming, and configuration.
• Work with RTL implemented in VHDL and SystemVerilog.
• Run verification regressions and debug RTL development.

Connaissances

SystemVerilog

ASIC verification

Mixed-signal verification

RTL reading (SV/VHDL)

Debugging & waveform analysis

Outils

SystemVerilog

VHDL

SDF back-annotation

UVM

Description du poste

Job Description

Job Description

Position Overview

Talent 101 is seeking an experienced Digital Design Verification Engineer to support mixed-signal semiconductor devices in which relatively small digital blocks operate closely with analog circuitry. The digital logic is generally under 10,000 gates and is used primarily for functions such as test-mode communication, control, and memory programming used to trim and configure analog circuits.

Although the digital designs are relatively small, the verification work requires careful attention to detail. The digital logic sits 'in between analog,' and requirements may not always exist as a fully defined standalone digital specification. The engineer must be able to communicate effectively with analog designers, understand device behavior, interpret existing implementations, and translate those requirements into a complete verification plan.

Key Responsibilities

• Learn and understand an existing SystemVerilog-based digital verification environment and its architecture.
• Review and execute test cases from previous related projects as part of project ramp-up.
• Understand the new device requirements through existing designs, documentation, RTL, and direct communication with analog design engineers.
• Develop a comprehensive testcase list and verification plan for the new device.
• Implement, debug, and maintain the SystemVerilog verification testcase suite.
• Modify or extend the existing DV environment as required for the new design.
• Verify small digital blocks used for test-mode communication, memory programming, analog trimming, configuration, and control.
• Work with RTL implemented in a combination of VHDL and SystemVerilog.
• Support reuse and modification of IP originating from multiple existing projects.
• Run verification regressions and debug failures throughout RTL development.
• After RTL verification, run and debug gate-level/netlist simulations, including SDF back-annotated timing simulations.
• Work closely with digital and analog designers to resolve ambiguous requirements and corner cases.
• Candidates with AMS experience may also run or support top-level mixed-signal simulations.

Required Qualifications

• Hands-on digital design verification experience for ASIC, mixed-signal IC, or semiconductor designs.
• Strong SystemVerilog verification experience.
• Ability to learn, understand, and modify an existing verification environment rather than requiring a greenfield environment.
• Experience creating verification plans and test case lists from design requirements.
• Strong regression execution, debugging, waveform analysis, and root-cause skills.
• Ability to read and understand RTL written in SystemVerilog and VHDL.
• Experience working with reused or modified RTL/IP from previous projects.
• Experience with gate-level/netlist simulation and SDF back-annotation, or the technical background to perform this work.
• Strong communication skills and ability to work directly with analog and digital designers where specifications may be incomplete or evolving.

Preferred Qualifications

• Verification experience on mixed-signal or analog-centric IC products.
• Experience verifying digital control, test-mode, trim, fuse, OTP, NVM, register, or memory-programming logic associated with analog circuits.
• Experience with AMS or mixed-signal simulation.
• Experience with SystemVerilog Assertions (SVA), functional coverage, constrained-random verification, or UVM where applicable.
• Experience debugging gate-level timing simulations and SDF-related issues.
• Experience working in environments where digital specifications are developed collaboratively with analog designers.
• Experience adapting verification IP or testbenches across multiple derivative semiconductor products.

Company Description

Talent 101 is a global services provider for the semiconductor industry only. We provide a total workforce or project turnkey solution anywhere you need it: onshore, nearshore, or offshore.

Company Description

Talent 101 is a global services provider for the semiconductor industry only. We provide a total workforce or project turnkey solution anywhere you need it: onshore, nearshore, or offshore.