Mixed-Signal Verification Engineer: IC Testbenches & Debug

Allegro MicroSystems; Manchester (NH); On-site; USD 95,000 - 135,000; Full time

Job summary

Allegro MicroSystems seeks a Mixed-Signal Design Verification (MSDV) Engineer to develop and execute top‑level verification testbenches for automotive/industrial ICs. You’ll bridge transistor‑level analog blocks and digital control, running functional simulations across power sequencing and system‑level tests.

You will verify power sequences, design‑level interaction, and testbench coverage while collaborating with Analog, Digital, and Systems teams to ensure first‑pass silicon success in a

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 1–3 years of industry or relevant academic/internship experience in mixed‑signal design verification or IC design.
• Familiarity with Cadence EDA tools (Virtuoso, ADE Explorer/Assembler, AMS Designer).
• Understanding of HDL languages (Verilog, SystemVerilog) and introductory knowledge of Verilog‑A/AMS.
• Solid grasp of fundamental analog circuits (amplifiers, bandgaps, LDOs, ADCs, oscillators) and digital logic basics.
• Basic familiarity with Linux environments and scripting (Python, Bash, or Skill) is a plus.
• Exposure to issue‑tracking tools (e.g., GitLab) and requirements management systems (e.g., Jama Connect).
• Curious, proactive problem‑solver with strong written and verbal communication skills who enjoys learning and collaborating in a global engineering environment.

Responsibilities

• Run and debug top‑level AMS simulations using Cadence AMS Designer and Virtuoso to verify chip‑level interactions between analog front‑ends and digital logic.
• Assist in writing and maintaining behavioral models and testbenches using Verilog, SystemVerilog, and Verilog‑AMS/Real‑Number Modeling (RNM/wreal).
• Verify power‑up/power‑down sequences, brown‑out events, and reset circuitry (POR, POK, UVLO) across voltage and temperature corners to ensure proper start‑up behavior.
• Validate register maps, EEPROM configuration loads, read/write protocols, and trim test modes against design specifications.
• Log and track verification bugs using GitLab issue tracking, applying standard workflow states (Analysis Pending, Verified) to support tapeout readiness.
• Partner with Analog Design, Digital Design, and Systems Engineering to review coverage metrics in Jama Connect and support testcase closure.

Skills

Verilog

SystemVerilog

Analog/digital design fundamentals

Problem solving

Communication skills

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline

Tools

Cadence Virtuoso

Cadence AMS Designer

ADE Explorer/Assembler

Jama Connect

GitLab

Job description

Allegro MicroSystems seeks a Mixed-Signal Design Verification (MSDV) Engineer to develop and execute top‑level verification testbenches for automotive/industrial ICs. You’ll bridge transistor‑level analog blocks and digital control, running functional simulations across power sequencing and system‑level tests.

You will verify power sequences, design‑level interaction, and testbench coverage while collaborating with Analog, Digital, and Systems teams to ensure first‑pass silicon success in a