ASIC Design Engineer — Digital/Analog & Low Power

Qualcomm; Santa Clara (CA); On-site; USD 107,000 - 161,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA, is seeking an ASIC Engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP for high performance, low power products.

You'll collaborate across software and hardware teams to meet system requirements, evaluate design flows, and utilize tools like RTL to GDS Flow and Virtuoso to deliver single-block/SoC designs with thorough documentation.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC design/verification experience.
• Master's degree in Science, Engineering, or related field with 1+ year of ASIC design/verification experience.
• PhD in Science, Engineering, or related field.

Responsibilities

• Defines, models, designs, optimizes, verifies, validates, implements, and documents IP for high performance, low power products.
• Creates architectures, circuit specs, logic designs, and system simulations from requirements.
• Collaboration across software/hardware teams to meet system requirements and customer needs.
• Evaluates process flow from high level design to synthesis, place & route, timing, and verification.
• Utilizes RTL to GDS Flow and Virtuoso to enable architecture/design of blocks/SoCs.
• Writes detailed technical documentation for EDA/IP/ASIC projects.

Skills

ASIC design

Verification

Validation

Integration

Scripting

SystemVerilog

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

RTL to GDS Flow

Virtuoso

Python

Perl

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA, is seeking an ASIC Engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP for high performance, low power products.

You'll collaborate across software and hardware teams to meet system requirements, evaluate design flows, and utilize tools like RTL to GDS Flow and Virtuoso to deliver single-block/SoC designs with thorough documentation.