Senior ASIC Architect – High-Performance IP/SoC

Qualcomm; Tempe (AZ); On-site; USD 180,000 - 270,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced ASIC Engineer to define, model, design (digital/analog), optimize, verify, validate, implement, and document IP development for high-performance, low-power products.

You will collaborate with software/hardware teams to determine execution paths and delivery milestones. Engagement spans from high-level design through synthesis and layout, with a focus on quality and documentation; leadership expectations include guidance to peers and

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 8+ years of ASIC design/verification experience.
• Master's degree in Science, Engineering, or related field with 7+ years of ASIC design/verification experience.
• PhD in Science, Engineering, or related field with 6+ years of ASIC design/verification experience.

Responsibilities

• Leverages expert ASIC knowledge to define, model, design (digital/analog), optimize, verify, validate, implement, and document IP development for high-performance blocks/SoCs.
• Creates architectures, circuit specs, and system simulations based on requirements.
• Collaborates with software/hardware, product management, and program management to meet system and customer needs.
• Acts as an expert resource for design/verification flow from high-level design to place-and-route and timing/power analysis.
• Writes detailed technical documentation for EDA/IP/ASIC projects and reviews documentation.

Skills

ASIC design

ASIC verification

Education

Bachelor's degree

Master's degree

PhD in related field

Tools

Virtuoso

RTL to GDS Flow

Job description

Qualcomm Technologies, Inc. is seeking an experienced ASIC Engineer to define, model, design (digital/analog), optimize, verify, validate, implement, and document IP development for high-performance, low-power products.

You will collaborate with software/hardware teams to determine execution paths and delivery milestones. Engagement spans from high-level design through synthesis and layout, with a focus on quality and documentation; leadership expectations include guidance to peers and