Digital IP Design Intern – RTL-to-GDS

Micron Technology, Inc; Boise (ID); Hybrid; USD 27,000 - 40,000; Full time

Benefits offered by this job

Medical insurance

Dental plan

Vision plan

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Boise, Idaho is seeking an intern to assist in digital IP design for DRAM products.

You will work with experienced engineers on RTL-to-GDS design flows, verify circuits, and contribute to silicon validation activities across AI-enabled tooling environments. The internship emphasizes hands-on experiences with EDA tools, cross-functional collaboration, and exposure to semiconductor development processes.

Qualifications

• Currently pursuing a Bachelor's or Master's in Electrical/Computer/Semiconductor Engineering or related STEM field.
• Completed coursework in CMOS Digital Circuits, SystemVerilog/UVM, and STA.
• Experience with Python or similar scripting languages and problem-solving skills.

Responsibilities

• Support design, development, and verification of digital IP circuits for next-generation DRAM products using RTL-to-GDS methodologies.
• Perform circuit analysis across PVT corners to evaluate performance, quality, and reliability.
• Develop automation scripts and leverage AI-assisted tools to improve engineering productivity and design quality.
• Collaborate with multi-functional teams on design implementation, verification, and silicon validation.
• Present technical findings and recommendations to engineering leadership and customers.

Skills

SystemVerilog/UVM

Python

Analytical thinking

Effective communication

Education

Electrical Engineering degree

Semiconductor Engineering coursework

Tools

EDA tools

Job description

Micron Technology, Inc. in Boise, Idaho is seeking an intern to assist in digital IP design for DRAM products.

You will work with experienced engineers on RTL-to-GDS design flows, verify circuits, and contribute to silicon validation activities across AI-enabled tooling environments. The internship emphasizes hands-on experiences with EDA tools, cross-functional collaboration, and exposure to semiconductor development processes.