DRAM IP Circuit Design Intern — Analog & AI-Driven

Socket.dev

Boise (ID)

On-site

USD 28,000 - 50,000

Part time

14 days+
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Job summary

Micron Technology invites interns to join the DRAM Engineering Group, IP Development, to contribute to DRAM IP development and verification. You will work on analog, mixed-signal, and high-speed interface circuits, gaining hands-on experience with SPICE and Verilog simulations and collaborating with cross-functional teams to ensure design quality.

As an intern, you will support schematic/layout reviews, parasitic extraction, post-layout validation, and automation scripting, while exploring

Qualifications

  • Pursuing a degree in Electrical/Computer/Semiconductor Engineering or related STEM field.
  • Strong coursework in CMOS analog/digital circuits and signal integrity.
  • Basic programming experience with Python, Perl, TCL, MATLAB or similar.

Responsibilities

  • Assist in design, development, and optimization of DRAM IP analog/mixed-signal/high-speed interface circuits.
  • Perform circuit simulations across process/voltage/temperature using SPICE/Verilog.
  • Support schematic development, layout review, parasitic extraction, and post-layout verification.
  • Collaborate with verification and layout teams to meet project objectives and improve design quality.
  • Develop automation scripts and AI workflows to enhance productivity and analysis quality.

Skills

Electrical Engineering
Computer Engineering
Semiconductor Engineering
Python
Teamwork

Education

Bachelor's in Electrical Engineering
Master's in Electrical Engineering
Ph.D. in Electrical Engineering

Tools

SPICE
Verilog

Job description

Micron Technology invites interns to join the DRAM Engineering Group, IP Development, to contribute to DRAM IP development and verification. You will work on analog, mixed-signal, and high-speed interface circuits, gaining hands-on experience with SPICE and Verilog simulations and collaborating with cross-functional teams to ensure design quality.

As an intern, you will support schematic/layout reviews, parasitic extraction, post-layout validation, and automation scripting, while exploring

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