Design Verification Engineer – Digital RTL & UVM

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); In loco; USD 90.000 - 130.000; Tempo pieno

Descrizione del lavoro

SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop testbenches, and drive pre‑ and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests with Python and MATLAB, and contribute to chip bring‑up and verification cycles.

The role requires a Bachelor's in EE/CS/CE and 1+ years of design verification and test bench development, with strong coding skills and willingness to work in a

Competenze

• Bachelor's in EE/CS/CE.
• 1+ years of design verification and test bench development with strong coding skills.

Mansioni

• Verify digital ASICs at block and system levels.
• Develop testbenches and drive pre- and post-silicon validation.
• Implement UVM or non-UVM test environments.
• Automate tests with Python and MATLAB.
• Contribute to chip bring-up and verification cycles.

Conoscenze

Testbench development

UVM environments

Coding skills

Formazione

Bachelor's in EE/CS/CE

Strumenti

Python

MATLAB

SystemVerilog

Descrizione del lavoro

SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop testbenches, and drive pre‑and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests with Python and MATLAB, and contribute to chip bring‑up and verification cycles.

The role requires a Bachelor's in EE/CS/CE and 1+ years of design verification and test bench development, with strong coding skills and willingness to work in a