Digital ASIC Design Engineer - Mixed-Signal IPs (DAC/ADC/PLL)

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Discretionary bonus program

Annual RSU grants

Comprehensive benefits package

Job summary

Qualcomm is seeking skilled RTL and ASIC design engineers to join the Mixed-Signal IP team. This role involves architecting, designing, and validating complex mixed-signal IP blocks, contributing to Qualcomm’s diverse product portfolio.

The ideal candidate should possess a Master's degree in Electrical Engineering and have at least 3 years of experience in RTL and ASIC design, working closely with other teams to ensure successful integration and performance.

Qualifications

• 3+ years of experience in RTL and ASIC design.
• Proficiency with industry-standard front-end ASIC design tools.
• Strong background in low-power digital design techniques.

Responsibilities

• Architect and define digital design for Mixed-Signal IPs.
• Develop micro-architecture and implement RTL for complex IP blocks.
• Collaborate with design verification teams to verify and fix designs.

Skills

RTL and ASIC design

Digital signal processing

Power Compiler

VCS

Design-for-test

Education

Master’s degree in Electrical Engineering

Bachelor's degree in Science or Engineering

Tools

Fusion Compiler

PrimeTime

Spyglass

Job description

Qualcomm is seeking skilled RTL and ASIC design engineers to join the Mixed-Signal IP team. This role involves architecting, designing, and validating complex mixed-signal IP blocks, contributing to Qualcomm’s diverse product portfolio.

The ideal candidate should possess a Master's degree in Electrical Engineering and have at least 3 years of experience in RTL and ASIC design, working closely with other teams to ensure successful integration and performance.