Digital ASIC Design Engineer for Mixed-Signal IPs

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Discretionary bonus program

Annual RSU grants

Comprehensive benefits package

Job summary

Qualcomm is seeking skilled RTL and ASIC design engineers to join the Mixed-Signal IP team. This role involves architecting, designing, and validating complex mixed-signal IP blocks, contributing to Qualcomm’s diverse product portfolio.

The ideal candidate should possess a Master's degree in Electrical Engineering and have at least 3 years of experience in RTL and ASIC design, working closely with other teams to ensure successful integration and performance.

Qualifications

• 3+ years of experience in RTL and ASIC design.
• Proficiency with industry-standard front-end ASIC design tools.
• Strong background in low-power digital design techniques.

Responsibilities

• Architect and define digital design for Mixed-Signal IPs.
• Develop micro-architecture and implement RTL for complex IP blocks.
• Collaborate with design verification teams to verify and fix designs.

Skills

RTL and ASIC design

Digital signal processing

Power Compiler

VCS

Design-for-test

Education

Master’s degree in Electrical Engineering

Bachelor's degree in Science or Engineering

Tools

Fusion Compiler

PrimeTime

Spyglass

Job description

Company

Qualcomm Technologies, Inc.

Overview

The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs — including DAC, ADC, and PLLs — for integration across Qualcomm’s product portfolio. In this role, you will collaborate with a cross-functional team to architect, design, implement, and validate complex IP blocks. Your work will directly support multiple business units and require a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.

Responsibilities

• Architect and define the digital design of Mixed-Signal IPs (e.g., DAC, ADC, PLL) in close collaboration with system architecture and analog design teams
• Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
• Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
• Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design-for-test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
• Design and analyze DFT logic, including ATPG for stuck‑at fault (SAF) and transition delay fault (TDF) coverage
• Create comprehensive design documentation, including hardware specifications
• Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
• Work with the physical design (PD) team to support floorplanning, placement, and timing closure of IPs
• Support SoC integration and debug, including pre‑silicon simulation and post‑silicon bring‑up

Required for this Role

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 3+ years of experience in RTL and ASIC design
• Proficiency with industry-standard front‑end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, Spyglass, and others

Preferred Qualifications

• Ph.D. in Electrical Engineering with 5+ years of industry experience in high-speed digital circuit design
• Strong background in low-power digital design techniques
• 2+ years of hands‑on experience in RTL design and ASIC implementation of mixed-signal IPs such as SerDes DDR PHY, PLLs, DACs, ADCs, and sensors
• Expertise in computer architecture, digital signal processing, and algorithm development
• Experience developing automation scripts and design productivity tools using Python or Perl

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
• PhD in Science, Engineering, or related field

EEO Statement

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Compensation

Pay range: $115,600.00 - $173,400.00. In addition to base salary, the position may include a competitive annual discretionary bonus program and opportunity for annual RSU grants. Additional benefits are available under Qualcomm’s comprehensive benefits package.