DFT Engineer

Akaasa Technologies; Menlo Park (CA); On-site; USD 103,000 - 165,000; Part time

Job summary

Akaasa Technologies seeks an experienced DFT Engineer in Menlo Park, CA to define, architect, and execute robust Design-for-Test strategies for high‑performance SoCs and ASICs. You will collaborate with front-end, physical design, verification, product, and test teams to achieve high test coverage and enable efficient post-silicon manufacturing test.

The ideal candidate has hands-on experience with scan, ATPG, MBIST, JTAG/IEEE 1149.1, DFT validation, and post-silicon bring-up, plus strong

Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development.
• Strong Verilog/SystemVerilog for DFT integration and debugging.
• Experience with scan insertion, scan synthesis, and boundary scan.

Responsibilities

• Define, architect, and execute robust DFT strategies for high-performance SoCs and ASICs.
• Collaborate with front-end design, physical design, verification, product, and test teams to achieve high test coverage.
• Enable efficient post-silicon manufacturing test.

Skills

DFT engineering

Verilog/SystemVerilog

Scan insertion

Scan synthesis

Scan compression

Boundary scan

ATPG patterns

MBIST

JTAG/IEEE 1149.1

Post-silicon bring-up

Debugging & problem-solving

Collaboration across teams

Job description

DFT Engineer

Location: Menlo Park, CA Onsite
Duration: Contract
Interview: Virtual

Note:
LinkedIn with location (before 2022)

Local or within 1 hour drive

Job Description

Our client is seeking an experienced DFT Engineer to define, architect, and execute robust Design-for-Test (DFT) strategies for high-performance SoCs and ASICs. The DFT Engineer will work closely with front-end design, physical design, verification, product engineering, and test engineering teams to achieve high test coverage, ensure silicon quality, and enable efficient post-silicon manufacturing test.

The ideal candidate will have hands-on experience with Scan, ATPG, MBIST, JTAG/IEEE standards, DFT validation, and post-silicon bring-up, along with strong Verilog/SystemVerilog skills.

Required Skills & Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development environments.
• Strong proficiency in Verilog/SystemVerilog for DFT integration, wrapper development, and simulation/debugging.
• Hands-on experience with scan insertion, scan synthesis, scan compression, and boundary scan.
• Experience with compressed scan architectures such as EDT/SmartTest.
• Strong experience generating, debugging, and fault-grading ATPG patterns for Stuck-at, At-Speed, Transition, and other fault models.
• Hands-on experience with MBIST insertion, MBIST architecture, and memory repair schemes.
• Solid understanding of JTAG and IEEE 1149.1, including TAP controllers and chip/board-level test logic.
• Experience supporting post-silicon DFT bring-up, pattern execution, silicon debug, and production yield ramp.
• Strong debugging, analytical, and problem-solving skills.
• Ability to collaborate effectively with design, verification, physical design, product, and test engineering teams.

Preferred Skills

• Experience with Tcl, Python, or Perl for DFT flow automation and scripting.
• Knowledge of advanced DFT techniques, including High-Speed I/O testing, SerDes loopback, and Analog DFT.
• Familiarity with synthesis tools such as Synopsys Design Compiler and Cadence Genus.
• Understanding of Static Timing Analysis (STA) and creation of timing constraints for DFT modes.
• Experience working with advanced semiconductor process nodes and high-performance SoC/ASIC designs.