DFT Engineer

Mirafra Technology; Tempe (AZ); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading software service organization in Tempe, Arizona seeks a qualified individual with extensive experience in design for test (DFT) for ASICs. The ideal candidate will possess at least 10 years of DFT experience for large scale ASICs and knowledge of Mentor Graphics tools. Responsibilities include generating ATPG, analyzing coverage results, and running gate simulations to verify functionality. Competitive compensation and a dynamic work environment are offered.

Qualifications

• 5 years of experience in DFT in ASICs required.
• 10 years of experience in DFT for large scale ASICs preferred.

Responsibilities

• Generate ATPG and analyze coverage results.
• Run gate simulation to verify scan patterns.

Skills

Design for test (DFT) structures knowledge

Gate simulation

ATPG generation and analysis

Tools

Mentor Graphics DFT tools

Job description

About Mirafra : Mirafra is a software service-based organization started in 2004. We are 500+ employees in India and 250+ in the US. Clear visibility to senior management helps for constant professional growth.

Job Description

Need knowledge of design for test (DFT) structures such as scan chains, scan compression and verification concepts for test coverage (ATPG). Be able to generate ATPG and analyze coverage results and how to extend or optimize them. Need to know how to run gate simulation to verify scan patterns and demonstrate functionality.

Minimum Qualifications

5 years experience in DFT in ASICs.

Qualifications

• 10 years experience in DFT for large scale ASICs. Experience with Mentor Graphics DFT tools.

Additional Information

All your information will be kept confidential according to EEO guidelines.