ASIC DFT Engineer

Broadcom; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grants

401(k) matching

ESPP

Job summary

Broadcom's ASIC Product Division (APD) is seeking a DFT specialist to lead end-to-end DFT programs for advanced silicon. You will drive DFT architecture, pattern generation, and verification, coordinating with Physical Design, STA and external customers.

The role requires strong DFT, scan, BIST and ATPG expertise and hands-on debugging across multi-disciplinary teams. Responsibilities include instrumenting test vectors, ATE bring-up, silicon yield improvement, and interfacing with test

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field; 8+ years of related experience or Master’s with 6+ years.

Responsibilities

• Lead DFT programs from specification to implementation and verification in ASIC products.
• Develop and verify DFT patterns and vectors for chip test coverage.

Skills

DFT background

ATPG vector generation

Verilog testbench

Memory BIST

Scan insertion

I/O DFT

Pattern generation

Debug and yield

IEEE1149.1/1149.6

TetraMax/Fastscan

Education

Bachelor's degree in relevant field

Master's degree (optional)

Tools

DFT Compiler

Mentor TestKompress

TT Xcell/ATE tools

TetraMax

Verilog simulators

Job description

USA-Colorado-Fort Collins-4380 Ziegler Road

USA-CA San Jose Innovation Drive

Full time

R025568

Job Description

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for APD's designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

Responsibilities

• Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC

• Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration

• Responsibilities includes pattern generation & Verification at chip level, Rapid bring-up at ATE and RMA support

• Working closely with STA and DI Engineers design closure for test

• Generating, Verifying & Debugging Test vectors before tape release.

• Validating & Debugging Test vectors on ATE during the silicon bring up phase

• Assisting with silicon failure analysis, diagnostics & yield improvement efforts

• Interfacing with the customer, physical design and test engineering/manufacturing teams located globally

• Working closely with I/P DFT engineers & other stakeholders

• Debugging customer returned parts on the ATE

• Innovating newer DFT solutions to solve testability problems in 3nm & beyond

• Automating DFT & Test Vector Generation flows

Skills/Experience

• Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)

• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)

• Logic BIST design and debug experience

• Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)

• Experience in Verilog coding, testbench generation & simulation

• Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)

• Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6

• Basic knowledge Test-STA and constraints

• Strong background on IEE1687, IJTAG, ICL and PDL

• The ability to work in a multi-disciplined, cross-department environment

• Solid knowledge in analog and digital circuit design, and device physics fundamentals

• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles

• Excellent problem solving, debug, root cause analysis and communication skills

• Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics

• Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.

• Experience working on ATE is a plus

• Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus

• Experience working on Tessent SSN is a plus

Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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