DFT Engineer

Broadcom; Austin (TX); On-site; USD 129,400 - 207,000; Full time

Benefits offered by this job

Equity grants

Annual bonus

401(k) match

Comprehensive health benefits

Job summary

Broadcom is seeking a senior DFT engineer to lead MBIST, scan insertion, ATPG, ATE pattern development, and yield analysis on advanced silicon.

You will collaborate across ATE, design, verification, and product teams during silicon bring-up, driving DFT methodology and tool usage to improve production yields.

Qualifications

• Requires extensive experience in silicon bring-up and yield improvement.
• Solid understanding of DFT techniques and ATPG.
• Proven RTL lint checking, scan compression and scan insertion experience.
• Experience with MBIST architecture and insertion.
• Strong debugging of simulation failures and digital logic fundamentals.

Responsibilities

• Collaborate with ATE on yield improvement and analysis.
• Develop ATE patterns, manage hand-off, and perform silicon debugging.
• Participate in block and chip-level DFT implementation.
• Work on DFT lint checking, MBIST architecture, logic insertion, scan insertion.
• Perform ATPG and pattern simulation for MBIST and scan.
• Coordinate with design, verification, and implementation teams during DFT design phase.

Skills

DFT techniques

scripting (Perl)

communication skills

STA constraint development

DFT tool usage

Education

BSEE

MSEE

Tools

Mentor Tessent

Synopsys DFT tools

Job description

Job Description

As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.

Key Responsibilities

• Work closely with the ATE engineer on yield improvement and analysis.
• Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
• Participate in block and chip-level DFT implementation, developing and executing all related tasks.
• Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
• Perform ATPG and pattern simulation for both MBIST and scan.
• Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
• Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.

Required Qualifications

• BSEE with 12+ years of relevant engineering experience or MSEE with 8+ years of relevant engineering experience.
• Required experience in silicon bring-up and yield improvement.
• Solid understanding of DFT techniques.
• Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
• Experience in MBIST architecture and insertion.
• Experience in analyzing and debugging simulation failures.
• Solid understanding of digital logic fundamentals.
• Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
• Proficiency with Perl or other scripting languages.
• Strong communication and interpersonal skills.
• Plus: Experience in STA constraint development in DFT modes.

Compensation and Benefits

The annual base salary range for this position is USD 129,400.00 To USD 207,000.00.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental, and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.