DFT Implementation Engineer

Intel; Austin (TX); On-site; USD 141,910 - 200,340; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Paid time off

Job summary

Intel's Austin campus seeks a DFT Design Engineer to shape silicon solutions by integrating DFT into cutting-edge SoCs and IPs. You will collaborate with architecture, design, verification, and manufacturing teams to drive innovation and optimize test coverage, power, performance, and area.

You will develop RTL/structural code for DFT features such as SCAN, MBIST, and BSCAN, provide timing closure, and support IP/SoC integration.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering.
• 5+ years in DFT/SoC design or related semiconductor areas.
• Experience with RTL design using Verilog/VHDL/SystemVerilog.

Responsibilities

• Develop RTL/structural code for DFT features (SCAN, MBIST, BSCAN).
• Provide timing closure support and test content generation for manufacturing.
• Collaborate on architecture/microarchitecture definitions for blocks/SoCs under DFT.
• Drive high test coverage and optimize power, performance, and area.
• Support IP/SoC integration and develop HVM content for ATE.

Skills

DFT concepts

RTL design

Verilog/SV

Python scripting

Cross-functional collaboration

Education

Bachelor's degree in EE/CE

Tools

Tessent

DFT Compiler

Modus

ISTK

Job description

The Role and Impact

As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency of Intel's products, ensuring seamless integration of Design for Test (DFT) capabilities in cutting-edge designs. This role offers the opportunity to collaborate with architecture, design, verification, and manufacturing teams, contributing to the creation of industry-leading SoC and IP solutions. Your work will drive innovation, enhance test coverage, and optimize the power, performance, and area of complex designs, enabling Intel's leadership in silicon design and manufacturing.

Job Details

Job Description:

The Role and Impact

As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency of Intel's products, ensuring seamless integration of Design for Test (DFT) capabilities in cutting-edge designs. This role offers the opportunity to collaborate with architecture, design, verification, and manufacturing teams, contributing to the creation of industry-leading SoC and IP solutions. Your work will drive innovation, enhance test coverage, and optimize the power, performance, and area of complex designs, enabling Intel's leadership in silicon design and manufacturing.

Key Responsibilities

• Develop logic design and register transfer level (RTL) coding to support DFT features such as SCAN, MBIST, and BSCAN.
• Provide timing closure support and test content generation for manufacturing.
• Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT.
• Optimize designs to meet power, performance, area, timing, and test coverage goals while adhering to design integrity standards.
• Write, integrate, and verify RTL and structural code for DFT functionality.
• Drive verification efforts to ensure architecture and microarchitecture specifications are achieved.
• Support IP and SoC integration to ensure high-quality implementation of DFT blocks.
• Develop high-volume manufacturing (HVM) content for rapid bring‑up and production on automatic test equipment (ATE).
• Collaborate with post‑silicon and manufacturing teams to verify features on silicon and document learnings for continuous improvement.
• Drive high test coverage through structural and IP‑specific tests to achieve product quality and defect‑per‑million (DPM) objectives.

Qualifications

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

5+ years of experience in DFT, SoC design, or related semiconductor design areas

Tessent Shell flows and SSN methodology

Hands‑on experience with ATPG, scan insertion, and/or MBIST/repair

RTL design experience using hardware description languages such as Verilog, VHDL, or SystemVerilog

Preferred Qualifications

Tessent Fast IO, ISTK, and related methodologies

Exposure to or interest in large ASIC applications in design or test

Familiarity with advanced DFT techniques for low‑power and high‑performance SoC designs

Understanding of industry standards such as IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), IEEE 1500 (Core Test), and IEEE 1838

Experience with industry‑standard DFT tools such as Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, or Cadence Modus

Proficiency in scripting languages such as TCL, Perl, or Python for design automation

Knowledge of timing constraints, UPF, and low‑power design and test methodologies

Experience working across cross‑functional teams or contributing to complex SoC projects

Take the next step in your career journey by joining Intel's innovative team. Start driving meaningful change in the world of technology today.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Texas, Austin

Additional Locations

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.