DFT Engineer

Match Point Solutions; Menlo Park (CA); On-site; USD 69,000 - 96,000; Full time

Job summary

MatchPoint Solutions is seeking a DFT Engineer in Menlo Park to architect and implement DFT strategies for high-performance SoCs/ASICs. You will collaborate with front-end, physical design, verification, and product engineering teams to ensure high test coverage and strong silicon quality.

Required experience includes 3+ years in DFT, Verilog/SystemVerilog, ATPG/MBIST, and JTAG, with familiarity in industry tools such as SpyGlass, Tessent, Modus, or TetraMAX.

Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
• Proficient in Verilog/SystemVerilog for DFT integration and debugging.
• Experience with ATPG/MBIST/JTAG and post-silicon support activities.

Responsibilities

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG/IEEE standards.
• Perform Scan Chain Insertion and optimization for timing closure and power grid compatibility.
• Translate pre-silicon patterns to tester formats and support post-silicon bring-up.
• Collaborate with PTE teams to optimize test time and boost manufacturing yield.

Skills

Verilog/SystemVerilog

Scan Insertion

ATPG

MBIST

JTAG

Post-Silicon Support

Scripting (Tcl/Python/Perl)

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Synopsys Design Compiler

Cadence Genus

Job description

MatchPoint Solutions is a fast-growing, young, energetic global IT-Engineering services company with clients across the US. We provide technology solutions to various clients like Uber, Robinhood, Netflix, Airbnb, Google, Sephora, and more! More recently, we have expanded to working internationally in Canada, China, Ireland, UK, Brazil, and India. Through our culture of innovation, we inspire, build, and deliver business results, from idea to outcome. We keep our clients on the cutting edge of the latest technologies and provide solutions by using industry-specific best practices and expertise.

Job Title: DFT Engineer

Location: (Remote / Hybrid / On-site City, Country) Menlo Park

Employment Type: (Full-time / Part-time / Contract) Contract

Pay Range: 50-70/Hr

Reports to (optional) :

As a DFT Engineer you will be responsible for defining, architecting,
and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will
work closely with front-end design, physical design, verification, and product engineering teams
to ensure high test coverage, optimal silicon quality, and streamlined post-silicon
manufacturing test enablement.

Key Responsibilities

Pre-Silicon Execution:

Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST,
and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).
Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and
power grid compatibility.
Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory
test routines.
Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including
Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.
Execute Verilog/SystemVerilog simulations for gate-level DFT validation, ensuring timing
and vector cleanliness (SDF simulation).
Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT,
Tessent, Modus, or TetraMAX)

Post-Silicon Production & Bring-up:

Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for
ATE (Automatic Test Equipment) deployment.
Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern
conversion, and silicon failures.
Collaborate with Product and Test Engineering (PTE) teams to optimize test time,
diagnose failure modes, and boost manufacturing yield.

Required Qualifications

Experience: 3+ years of hands‑on DFT experience in advanced SoC/ASIC development
nodes.

Core Skills & Technical Expertise:

Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT
integration, wrapper creation, and simulation debugging.
Scan Insertion: Hands‑on experience with scan synthesis, compressed scan architectures (EDT/SmartTest), and boundary scan integration.
ATPG: Deep experience generating, debugging, and fault‑grading Stuck‑at, At‑speed, and fault‑model test patterns.
MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip level test logic integration.
Post‑Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.

Preferred Skills

Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.
Knowledge of advanced DFT concepts like High‑Speed IO testing, SerDes loopback, or
Analog DFT.
Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes

MatchPoint Solutions provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training.