Sr. DFT Design Engineer, AWS Machine Learning Acceleration

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,000 - 215,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in the United States is seeking a Sr. DFT Design Engineer to design and optimize DFT for advanced ASICs in Cloud-Scale ML acceleration.

You will collaborate with PD, Architecture, and Product Engineering to align schedules and deliver high-quality DFT from RTL to silicon. The role requires 5+ years in ASIC design, strong scripting skills, and in-depth DFT knowledge (ATPG, JTAG, MBIST).

Qualifications

• Bachelor's degree in computer science, electrical engineering, or related field.
• 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks.
• Knowledge about industry standard DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
• Experience with automation script development.

Responsibilities

• Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes.
• Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions.
• Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals.
• Mentor and develop junior engineers through code reviews, methodology training, and technical guidance.
• Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up.

Education

Bachelor's degree in CS/EE or related field

Master's or Ph.D. in EE/CS or related field

Tools

Perl

Python

Tcl

Job description

Description

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. Our success depends on world‑class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for a Sr. DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs.

Description

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. Our success depends on world‑class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for a Sr. DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs.

Key job responsibilities

• Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
• Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
• Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals
• Mentor and develop junior engineers through code reviews, methodology training, and technical guidance
• Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up

Basic Qualifications

• Bachelor's degree in computer science, electrical engineering, or related field
• 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience
• Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Experience with automation script development

Preferred Qualifications

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring-up and post-silicon validation
• MS degree in computer science, electrical engineering, or related field
• Experience with gate-level testing and multi-clock design practices (CDC)
• Good breadth of knowledge in chip design from micro-architecture through physical design
• Good knowledge of design verification (DV) simulation methodologies
• Strong programming and scripting skills in Perl, Python or Tcl
• Experience with industry standard DFT/SCAN/ATPG tools
• Experience with STA constraints development and analysis for DFT modes
• Practical experience with silicon debug

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The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

USA, TX, Austin - 159,200.00 - 215,300.00 USD annually

Company

- Annapurna Labs (U.S.) Inc.

Job ID: A10409021