DFT Design Engineer

Cadence; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Cadence is seeking a SoC/ASIC Digital Design Engineer with strong DFT experience to join our team in Austin, TX. You will work on scan chain insertion, compression scan, MBIST, and ATPG, with hands-on synthesis, verification, and debugging of Verilog testbenches.

Collaborate with cross-functional teams across Architecture, Design, and external customers to deliver robust DFT solutions while maintaining quality metrics and project timelines.

Qualifications

• 3–12 years of experience in SoC/ASIC Digital Design focused on DFT.
• Experience with scan chain insertion, compression scan, MBIST and ATPG.
• Hands-on synthesis, verification and debugging Verilog testbenches.
• Familiarity with JTAG 1149.1/6, IEEE1500 and IEEE1687.

Responsibilities

• Finish DFT tasks independently in fast-paced projects.
• Collaborate with cross-functional teams including Architecture and Design.
• Debug and analyze failures to improve fault coverage.

Skills

DFT

Scan chain insertion

Compression scan

MBIST

ATPG

JTAG 1149.1/6

IEEE1500

IEEE1687

Verilog testbenches

Synthesis & verification

Cadence tools

Tools

Cadence tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.Requirements;US citizenship preferred.Prior 3-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)Should possess intimate knowledge of DFT insertion flowsBasic scan chain insertion using synthesis or other software toolsExperience in compression scan insertion, LBIST and other scan technologiesIntimate knowledge of memory build-in self-test (MBIST)Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goalsDebug and Analysis of failures to improve fault coverageVerification of ATPG testbenches and debugging root cause of simulation mis-comparesWorking knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687Knowledge of timing analysis and equivalency checks would be added bonusAbility to work in collaborative team environmentPrior experience with Cadence tools and flows is highly desirableShould be able to finish DFT tasks independentlyStrong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problemsAbility to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External CustomersSelf-driven and committed individual who can work in a fast-paced project environmentWe're doing work that matters. Help us solve what others can't.

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