DFT & ATPG Engineer - Scan Insertion Specialist

Apple Inc.; Austin, Northern (TX, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. in Austin, Texas is seeking a DFT/ATPG design engineer to lead scan insertion and ATPG during the DFT design phase. You will work with DV, Front-End, PD and STA teams to resolve hardware design issues and deliver configurations for RTL generation.

You will also create infrastructure to improve design cycles and maintain high-quality pattern generation and coverage. The role requires a Master’s in Electrical/Electronics Engineering and 2 years of related experience, with strong Verilog

Qualifications

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
• 2 years of experience in the job offered or related occupation.
• Experience with Verilog RTL for DFT IP.
• Experience with RTL design for DFT features (scan codec, ATPG isolation, scan routing).
• Experience with scripting languages (Python, Perl, TCL) including automation of design flows, verification, synthesis and modeling.
• Experience with basic FE tools (CDC, RDC, Lint) and understanding of clock/reset domains.
• Experience with synthesis tools and configuring constraints for synthesis.
• Experience with ATPG tools for Scan DRC and ATPG coverage.
• Knowledge of computer architecture principles and SOC development flows for DFT analysis.
• Knowledge of Scan and MBIST DFT architecture and implementation concepts.

Responsibilities

• Lead scan insertion and ATPG during DFT design development.
• Deliver configs and scripts for RTL generation and scans.
• Debug and support Front-end team to ensure high-quality scan insertion.
• Support PD, STA and DV teams on scan-related issues.
• Improve ATPG flows to achieve higher stuck-at coverage.
• Collaborate with CAD team and tool vendors to resolve issues and improve flows.
• Debug simulations and silicon failures; implement RTL/script/config changes.
• Create infrastructure to improve design cycle and add new checks for RTL issues.
• Ensure compliance with specs across STA, physical, power and logic areas.

Skills

Verilog RTL for DFT

RTL Design for DFT

Scripting: Python/Perl/TCL

FE tools: CDC RDC Lint

Synthesis constraints/configs

ATPG for Scan DRC

ATPG coverage analysis

Computer architecture basics

Scan/MBIST DFT concepts

Education

Master's degree in Electrical/Electronics Engineering

Job description

Apple Inc. in Austin, Texas is seeking a DFT/ATPG design engineer to lead scan insertion and ATPG during the DFT design phase. You will work with DV, Front-End, PD and STA teams to resolve hardware design issues and deliver configurations for RTL generation.

You will also create infrastructure to improve design cycles and maintain high-quality pattern generation and coverage. The role requires a Master’s in Electrical/Electronics Engineering and 2 years of related experience, with strong Verilog