Lead DFT Engineer

Saur Energy International; West Virginia; On-site; USD 90,000 - 130,000; Full time

Job summary

Saur Energy International is seeking a Digital Design Engineer responsible for understanding the DFT architecture and delivering scan insertion collaterals to the implementation team. The role supports scan insertion flows during synthesis and requires proficiency with Mentor Tessent, Synopsys DFT Compiler, and Cadence Encounter Test.

Ideal candidates will contribute to ATPG at partition and SoC levels, and be familiar with GLS simulation tools and fault modeling.

Qualifications

• Experience with scan insertion and DFT architectures.
• Cannot exceed 140 chars

Responsibilities

• Understand DFT architecture and provide scan insertion collaterals to implementation team.
• Enable scan insertion flows during synthesis.
• Collaborate across functions to ensure DFT testability.

Skills

Scan insertion

ATPG

GLS

DFT tools proficiency

IEEE 1149.1 (JTAG)

IEEE 1687 (IJTAG)

Mentor Tessent

Synopsys DFT Compiler

Cadence Encounter Test

fault modeling

coverage analysis

Tools

Mentor Tessent

Synopsys DFT Compiler

Cadence Encounter Test

Job description

Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis. Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should have familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG). Effective communication and teamwork skills, with the ability to collaborate across functions.